Patents Examined by Walter D. Davis, Jr.
  • Patent number: 5488731
    Abstract: A multiprocessor system includes a plurality of substantially identical nodes interconnected through a switching network, each node including a disk drive, NVRAM, and a processor. The system stores data in either a RAID or mirrored fashion across a plurality of disk drives in different nodes. When data is stored in a RAID arrangement, an NVRAM in a parity node is provided with an entry including the new data, a copy of old data from the node to which the new data is to be written, a copy of the old parity, and a synchronization state indicator. The parity node determines new parity and transmits the new data to the data node for storage. Upon receiving an acknowledgement, the parity node resets the synchronization indicator. When power-up occurs, after a power failure, the parity node scans its NVRAM for any entry and upon finding one with a non-reset state indicator, transmits the new data to a destination data node for entry thereby synchronizing the contents of data and parity nodes.
    Type: Grant
    Filed: December 8, 1994
    Date of Patent: January 30, 1996
    Assignee: International Business Machines Corporation
    Inventor: Noah Mendelsohn
  • Patent number: 5483660
    Abstract: Method and apparatus for performing multiplexed and non-multiplexed bus cycles in a data processing system (10). The present invention allows a data processing system (10) to switch from multiplexed bus cycles to non-multiplexed bus cycles, and vice-versa, without requiring the data processing system (10) to be reset. In one embodiment of the present invention, a single user programmable control bit (90) is used to select whether an external bus cycle will be multiplexed or non-multiplexed. In more complex embodiments of the present invention, the ability to switch between multiplexed external bus cycles and non-multiplexed external bus cycles may be achieved by way of a plurality of user programmable register fields (96, 100, 102, and 104) located in registers 44. The plurality of user programmable register fields (96, 100, 102, and 104) may be associated with one or more chip select signals.
    Type: Grant
    Filed: November 29, 1993
    Date of Patent: January 9, 1996
    Assignee: Motorola Inc.
    Inventors: Oded Yishay, Joseph Jelemensky, Ann E. Harwood, Javier Saldana
  • Patent number: 5483658
    Abstract: A monitoring computer monitors the communications occurring within at least one communication system for at least one unique processing device identification code associated with a processing device. Upon detecting the at least one device identification code, the monitoring computer compares the type of application in use by the processing device with known software parameters (including the allowable types of applications and their serial numbers) for the processing device. When the type of application in use by the processing device does not substantially match the known software parameters for the processing device, the processing device is identified as using an unauthorized and/or duplicated software application.
    Type: Grant
    Filed: February 26, 1993
    Date of Patent: January 9, 1996
    Inventors: Gary W. Grube, Timothy W. Markison
  • Patent number: 5471627
    Abstract: A systolic array of processing elements is connected to receive weight inputs and multiplexed data inputs for operation in two dimension convolution mode, or fully-connected neural network mode, or in cooperative, competitive neural network mode. Feature vector or two-dimensional image data is retrieved from external data memory and is transformed via input look-up table to input data for the systolic array. The convoluted image or outputs from the systolic array are scaled and transformed via output look-up table for storage in the external data memory. The architecture of the system allows it to calculate convolutions of any size within the same physical systolic array, merely by adjusting the programs that control the data flow.
    Type: Grant
    Filed: May 26, 1992
    Date of Patent: November 28, 1995
    Assignee: HNC, Inc.
    Inventors: Robert W. Means, Horace J. Sklar
  • Patent number: 5454117
    Abstract: In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding.
    Type: Grant
    Filed: August 25, 1993
    Date of Patent: September 26, 1995
    Assignee: NexGen, Inc.
    Inventors: David L. Puziol, Korbin S. Van Dyke, Larry Widigen, Len Shar, Walstein B. Smith, III
  • Patent number: 5446916
    Abstract: A variable length codeword packer communicates codeword data in successive m-bit bytes. A binary sum is accumulated indicative of a total number of codeword bits received over time. A byte pointer is derived from at least one most significant bit of the binary sum. A bit pointer is derived from a plurality of least significant bits of the binary sum. A first data storage array has a plurality of m-bit first storage bytes and is responsive to the byte pointer for storing received codeword data in the first storage bytes. A second data storage array has a plurality of m-bit second storage bytes and is responsive to the byte and bit pointers for filling the second storage bytes with codeword data from the first data storage array. m-bit bytes of codeword data are output from each filled second storage byte to provide successive m-bit bytes of codeword data. The use of a multistage approach in packing variable length codewords substantially reduces the complexity as compared to single stage designs.
    Type: Grant
    Filed: March 26, 1993
    Date of Patent: August 29, 1995
    Assignee: GI Corporation
    Inventors: Henry Derovanessian, Vincent Liu
  • Patent number: 5418971
    Abstract: A system and method of sequencing commands for operation of a volume positioning mechanism in an automated library is taught. The automated library has a plurality of volumes, a plurality of racks for storing the plurality of volumes and at least a first drive unit for recording data to or reading data from a volume mounted thereon by the volume positioning mechanism. Exogenous requests for data stored to the volumes or for storing data to volumes are received from time to time by the library. Each exogenous request for data in a volume is utilized to generate at least a first command for execution by the volume positioning mechanism. Commands as generated are stored in a command queue having a queue input level, a queue output level for the next scheduled command for execution and allowing a plurality of intervening levels. With each introduction of a new command to the command queue, the command queue is reordered with a goal of improving time to dispatch for execution of high priority commands.
    Type: Grant
    Filed: April 20, 1992
    Date of Patent: May 23, 1995
    Assignee: International Business Machines Corporation
    Inventor: Wayne C. Carlson
  • Patent number: 5390335
    Abstract: A method for modifying system configuration data sets in a telecommunications switching system that has first function modules (SWU-ADS) for processing switching-oriented and/or administration and maintenance procedures and second peripheral function modules (VMS, ETB) for realizing supplementary performance features. For producing data consistency, backup copies are produced of the content of at least a part of the databases and administration and maintenance commands that modify database contents and that are subsequently input into the system, are listed in the form of command information in the chronological sequence of their occurrence. Every command information is supplemented with a database-associated information that indicates the implementation or non-implementation of the respective administration and maintenance command.
    Type: Grant
    Filed: July 21, 1992
    Date of Patent: February 14, 1995
    Assignee: Siemens Aktiengesellschaft
    Inventors: Luzia Stephan, Juergen Hoefner, Friedrich Woess