Abstract: An organic light-emitting display apparatus is provided. The display apparatus includes a pixel-defining layer disposed on a substrate, wherein the pixel-defining layer defines an emission region and a non-emission region, an organic light-emitting device disposed in the emission region, and a protruding portion disposed on a portion of the pixel-defining layer in the non-emission region. The display apparatus also includes a thin film encapsulating layer disposed on the substrate for sealing the organic light-emitting device and the protruding portion, the thin film encapsulating layer comprising at least one organic film and at least one inorganic film, wherein at least one organic film corresponds to a functional organic film, and a height of a first upper surface of the functional organic film disposed away from the protruding portion is lower than a height of a second upper surface of the functional organic film disposed near a top of the protruding portion.

Abstract: Method for producing a device with transistors distributed over several levels and provided with a resistive memory cell having an electrode formed of a conductor portion belonging to a connection element connected to a transistor of a given level.

Abstract: A display device includes a display region having a plurality of pixels, each of the plurality of pixels including a pixel electrode formed on an insulating surface, the plurality of pixels being arranged in a matrix shape, a bank covering an end of the pixel electrode, an organic layer including a light emitting layer covering respective light emitting regions on the pixel electrodes, an opposite electrode on the organic layer and the bank, and a first inorganic insulating layer on the opposite electrode, wherein each of the opposite electrode and the first inorganic insulating layer has a discontinuous region between the two adjacent light emitting regions.

Abstract: A memory device including first conductive lines spaced apart from each other and extending in a first direction; second conductive lines spaced apart from each other and extending in a second direction that is different from the first direction; first memory cells having a structure that includes a selection device layer, a middle electrode layer, a variable resistance layer, and a top electrode layer; and insulating structures arranged alternately with the first memory cells in the second direction under the second conductive lines, wherein the first insulating structures have a top surface that is higher than a top surface of the first top electrode layer, and the second conductive lines have a structure that includes convex and concave portions, the convex portions being connected to the top surface of the top electrode layer and the concave portions accommodating the insulating structures between the convex portions.

Abstract: An optoelectronic component for mixing electromagnetic radiation having different wavelengths, for example, for the far field is disclosed. In an embodiment the optoelectronic component includes a carrier, at least one first semiconductor chip arranged on the carrier and having a first radiation exit surface for emitting electromagnetic radiation in a first spectral range and at least one second semiconductor chip arranged on the carrier and having a second radiation exit surface for emitting electromagnetic radiation in a second spectral range, wherein a diffusing layer is arranged on the first and second radiation exit surfaces of the semiconductor chips that face away from the carrier and wherein a reflecting layer is arranged between the first semiconductor chip and the second semiconductor chip, the first and second radiation exit surfaces being free from the reflecting layer at least in regions.

Abstract: An imaging device and a manufacturing method of the imaging device are provided, which can lower the level of a dark current in an optical black pixel without forming a new layer such as a hydrogen diffusion preventing film. Both of an insulating layer over a photodiode arranged over an effective pixel region and an insulating layer over a photodiode arranged over an OB pixel region include silicon nitride, are formed of the same layer, and are coupled with each other.

Abstract: Methods and systems for improved matching for on-chip capacitors may comprise in a semiconductor die comprising an on-chip capacitor with one or more metal layers: electrically coupling a first set of metal fingers, electrically coupling a second set of metal fingers that are interdigitated with the first set of metal fingers, wherein the first set of metal fingers and the second set of metal fingers are arranged symmetrically in the semiconductor die, and configuring the on-chip capacitor in a plurality of symmetric sections, wherein a boundary between each of the plurality of sections is configured in a zig-zag pattern. The first set of metal fingers and the second set of metal fingers may be arranged with radial symmetry. A first set of metal fingers in a first metal layer may be electrically coupled to a set of metal fingers in a second metal layer.

Abstract: A silicon carbide (SiC) semiconductor element includes a semiconductor layer, a dielectric layer on a surface of the semiconductor layer, a gate electrode layer on the dielectric layer, a first doped region, a second doped region, a shallow doped region and a third doped region. The semiconductor layer is of a first conductivity type. The first doped region is of a second conductivity type and includes an upper doping boundary spaced from the surface by a first depth. The shallow doped region is of the second conductivity type, and extends from the surface to a shallow doped depth. The second doped region is adjacent to the shallow doped region and is at least partially in the first doped region. The third doped region is of the second conductivity type and at least partially overlaps the first doped region.

Abstract: A semiconductor device may include pipe channel layer, and a pipe gate surrounding the pipe channel layer. The semiconductor device may include an oxidization layer formed between the pipe gate and the pipe channel layer. The semiconductor device may include a source side channel layer and a drain side channel layer extended from the pipe channel layer to protrude further than the oxidization layer.

Abstract: The present invention prevents an optical device from malfunctioning or receiving a reduced amount of light due to a foreign object adhering to or floating above a light receiving portion of the optical device. A metal frame (31) includes at least one protruding section (34) that protrudes toward an LCOS element (11).

Abstract: The present invention relates to a device and method for generating an identification key using a process variation in a via process, and specifically the device for generating an identification key may include a first node provided in a semiconductor chip, a second node which is formed in a different layer from the first node, a via which is electrically shorted to the first node, and which is formed between the first node and the second node, the overlap distance between the second node and the via, in a pattern layout of the semiconductor chip, being adjusted to a value that is less than a threshold according to a design rule that ensures that the first node and the second node are shorted by the via, and a reader which provides an identification key by identifying whether the first node and the second node are shorted due to the via.

Abstract: A semiconductor device includes: a substrate on which a first contact portion is formed; a lower shield plate provided above the substrate to avoid the first contact portion and including a magnetic substance; a semiconductor chip provided above the lower shield plate and including a second contact portion electrically connected to the first contact portion, and a connection member that electrically connects the first contact portion and the second contact portion; and an upper shield plate provided above the semiconductor chip to avoid the second contact portion and the connection member and including a magnetic substance. An end of at least one of the lower shield plate and the upper shield plate is bent toward the other one of the lower shield plate and the upper shield plate so have a side wall portion whose tip is connected to the other one of the lower shield plate and the upper shield plate.

Abstract: A heat sink can include a fin using graphite, and a base with a high heat dissipation film formed on its surface to be provided with a high heat dissipation performance. The heat sink can include a base made of metal and a fin fixed to the base. The fin can include a graphite sheet. The base has a surface coated with a film having a higher heat dissipation property than that of the metal constituting the base. The film of the base is removed from at least the region where the fin is fixed, so that the fin is fixed to the metal constituting the base.

Abstract: An ultraviolet light emitting device having high quality and high reliability is provided by preventing deterioration of electrical characteristics which is associated with an ultraviolet light emission operation and caused by a sealing resin.

Abstract: A CMOS device with a plurality of PMOS transistors each having a PMOS drain and a plurality of NMOS transistors each having an NMOS drain includes a first interconnect on an interconnect level extending in a length direction to connect the PMOS drains together. A second interconnect on the interconnect level extends in the length direction to connect the NMOS drains together. A set of interconnects on at least one additional interconnect level couple the first interconnect and the second interconnect together. A third interconnect on the interconnect level extends perpendicular to the length direction and is offset from the set of interconnects to connect the first interconnect and the second interconnect together.

Abstract: A magnetic tunnel junction has a conductive first magnetic electrode comprising magnetic recording material. A conductive second magnetic electrode is spaced from the first electrode and comprises magnetic reference material. A non-magnetic tunnel insulator material is between the first and second electrodes. The magnetic recording material of the first electrode comprises a first magnetic region, a second magnetic region spaced from the first magnetic region, and a third magnetic region spaced from the first and second magnetic regions. A first non-magnetic insulator metal oxide-comprising region is between the first and second magnetic regions. A second non-magnetic insulator metal oxide-comprising region is between the second and third magnetic regions. Other embodiments are disclosed.

Abstract: A method of fabricating a structure including a high mobility backplane and a-Si photodiode imager includes forming a matrix of metal oxide thin film transistors on the surface of a rigid support member, depositing a planarizing layer on the matrix of transistors that is either porous or permissive/diffusive to oxygen at temperatures below approximately 200° C., and fabricating a matrix of passivated a-Si photodiodes over the matrix of transistors and electrically connected one each photodiode to each of the transistors. A continuous path is provided through the planarizing layer from the exterior of the structure to each of the transistors and the structure is annealed at a temperature below 200° C. in an oxygen ambient to move oxygen from the oxygen ambient to an active layer of each of the transistors and repair loss of oxygen damage to the transistors caused by the fabrication of the passivated a-Si photodiodes.

Abstract: Semiconductor devices with wider field gates for reduced gate resistance are disclosed. In one aspect, a semiconductor device is provided that employs a gate. The gate is a conductive line disposed above the semiconductor device to form transistors corresponding to active semiconductor regions. Each active semiconductor region has a corresponding channel region. Portions of the gate disposed over each channel region are active gates, and portions not disposed over the channel region, but that are disposed over field oxide regions, are field gates. A voltage differential between each active gate and a source of each corresponding transistor causes current flow in a channel region when the voltage differential exceeds a threshold voltage. The width of each field gate is a larger width than each active gate. The larger width of the field gates results in reduced gate resistance compared to devices with narrower field gates.

Abstract: Various implementations described herein may be directed to using inter-tier vias (IVs) in integrated circuits (ICs). In one implementation, a three-dimensional (3D) IC may include a plurality of tiers disposed on a substrate layer, where the tiers may include a first tier having a first active device layer electrically coupled to first interconnect layers, and may also include a second tier having a second active device layer electrically coupled to a second interconnect layer, where the first interconnect layers include an uppermost layer that is least proximate to the first active device layer. The 3D IC may further include IVs to electrically couple the second interconnect layer and the uppermost layer. The uppermost layer may be electrically coupled to a power source at peripheral locations of the first tier, thereby electrically coupling the power source to the first active device layer and to the second active device layer.

Abstract: Some embodiments of the present disclosure relate to a three dimensional integrated circuit (3DIC) structure. The 3DIC structure has a first die and a second die that is bonded to the first die by one or more bonding structures. The one or more bonding structures respectively have a first metal pad arranged on the first die and a second metal pad arranged on the second die. A first plurality of support structures are disposed between the first die and the second die. The first plurality of support structures include polymers and are laterally spaced apart from a closest one of the one or more bonding structures. The first plurality of support structures extend below an upper surface of the second metal pad.