Abstract: A substrate processing apparatus includes: a plasma generating unit to excite a process gas into plasma state; a process chamber where a substrate is processed using the process gas excited in plasma state; a loading port installed at a sidewall of the process chamber, wherein the substrate is passed through the loading port when the substrate is loaded into the process chamber; a substrate support supporting the substrate in the process chamber; an electrode unit installed in the substrate support and including a plurality of divided electrodes; an impedance adjusting unit electrically connected to each of the plurality of electrodes to adjust an impedance thereof; and a control unit to control the impedance of the impedance adjusting unit so as to adjust the electrical potentials of the respective electrodes of the electrode unit. The substrate processing apparatus improves the uniformity of a substrate during a substrate processing process using plasma.

Abstract: A semiconductor device is disclosed, comprising: a substrate; a semiconductor layer disposed on the substrate; a source electrode and a drain electrode disposed on the semiconductor layer, and a gate electrode disposed between the source electrode and the drain electrode; a dielectric layer disposed on at least a part of the surface of the semiconductor layer which is between the gate electrode and the drain electrode, the dielectric layer having at least a recess therein; and a source field plate disposed on the dielectric layer and at least partially covering the recess, the source field plate being electrically connected to the source electrode through at least a conductive path. A method of manufacturing such a semiconductor device is also disclosed.

Abstract: A power semiconductor device includes: a first MOSFET having a first conductivity type including a first source, a first drain, and a first gate; a second MOSFET having a first conductivity type including a second drain, a second source electrically coupled to the first source, and a second gate electrically coupled the first gate; and a diode being coupled between the first and second drains.

Abstract: A power line layout structure of a semiconductor device and a method for forming the same are disclosed. The power line layout structure of the semiconductor device includes a first block region including a plurality of first and second power lines, a second block region including a plurality of first and second power lines spaced apart from the first block region by a predetermined distance. Further, a first connection pattern arranged in a boundary region between the first and second block region, and formed to interconnect the first power line of the first block region and the first power line of the second block region. Still further, a second connection pattern arranged in a boundary region between the first and second block regions, and formed to interconnect the first and second block region power lines, wherein the first and second connection patterns are formed over different layers.

Abstract: Image sensors comprising an isolation region according to embodiments are disclosed, as well as methods of forming the image sensors with isolation region. An embodiment is a structure comprising a semiconductor substrate, a photo element in the semiconductor substrate, and an isolation region in the semiconductor substrate. The isolation region is proximate the photo element and comprises a dielectric material and an epitaxial region. The epitaxial region is disposed between the semiconductor substrate and the dielectric material.

Abstract: A liquid crystal display according to an exemplary embodiment of the present disclosure includes: a first substrate; a gate line formed on the first substrate and extended in a first direction; a data line extended in a second direction that is perpendicular to the gate line; switching elements connected to the gate line and the data line; a voltage-dividing reference voltage line connected to a switching element; a first sub-pixel electrode connected to a switching element; and a second sub-pixel electrode connected to a switching element, wherein the first sub-pixel electrode and the second sub-pixel electrode include one or more vertical stem parts formed on a left side or a right side thereof, and the voltage-dividing reference voltage line is formed to be parallel to the data line.

Abstract: A resin composition including an epoxy resin monomer, a novolac resin including a compound having a structural unit represented by Formula (I), and a filler; in which the filler has at least 4 peaks in a particle size distribution measured by laser diffractometry, in which four of the peaks are present respectively in ranges of not less than 0.01 ?m and less than 1 ?m, not less than 1 ?m and less than 10 ?m, from 10 ?m to 50 ?m, and from 20 ?m to 100 ?m, and in which a peak present in a range of from 10 ?m to 50 ?m includes an aluminum oxide particle, and a peak present in a range of from 20 ?m to 100 ?m includes a boron nitride particle. In Formula (I) each of R1, R2 and R3 independently represents a hydrogen atom, an alkyl group, or the like. m represents 0 to 2, and n represents 1 to 7.

Abstract: Integrated circuits and manufacturing methods of the same are disclosed. The integrated circuit includes a transistor, a first dielectric layer, an etch stop layer, a first via and a first conductive layer. The first dielectric layer is disposed between the transistor and the etch stop layer. The first via is disposed in the first dielectric layer and the etch stop layer, and electrically connected to the transistor. The first conductive layer is in contact with the first via, wherein the first via is disposed between the first conductive layer and the transistor, and the etch stop layer is aside a portion of the first via adjacent to the first conductive layer.

Abstract: A light emitting device including a light emitting element that has a peak light emission wavelength of from 400 nm to 455 nm, a first fluorescent material that has a peak fluorescence wavelength in the range of from 650 nm to 670 nm, and a second fluorescent material that has a peak fluorescence wavelength in the range of from 520 nm to 550 nm, wherein the light emitting device exhibits a light emission spectrum with an average light emission strength of 30% or less in the range of from 600 nm to 620 nm, when the maximum light emission strength in the range of from 520 nm to 550 nm is taken as 100%.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration. The APT feature is formed on the fin active region, spans between the first sidewall and the second sidewall, and has a first doping concentration.

Abstract: A method for manufacturing an array substrate which includes: depositing a gate metal film on a base substrate, and forming a first pattern including the gate electrode by a first patterning process; depositing a gate insulating film, a first transparent conductive film, a source/drain metal film and a doped a-Si film sequentially, and forming a second pattern including the pixel electrode, the source electrode, the drain electrode and a doped semiconductor layer by a second patterning process; depositing an a-Si film, and forming a third pattern including a TFT channel, the semiconductor layer and a gate insulating layer via-hole by a third patterning process; depositing a passivation layer film, and forming a fourth pattern including a passivation layer via-hole by a fourth patterning process, the passivation layer via-hole being arranged at a position corresponding to the gate insulating layer via-hole; and depositing a second transparent conductive film on the base substrate with the fourth pattern, and f

Abstract: Three-dimensional (3D) non-volatile memory arrays having a vertically-oriented thin film transistor (TFT) select device and method of fabricating such a memory are described. The vertically-oriented TFT may be used as a vertical bit line selection device to couple a global bit line to a vertical bit line. A select device pillar includes a body and upper and lower source/drain regions. At least one gate is separated horizontally from the select device pillar by a gate dielectric. Beneath each gate, a single gap fill dielectric layer extends vertically from a lower surface of the gate, at least partially separating the gate from the underlying global bit line. Between horizontally adjacent pillars, this same dielectric layer extends from its same lower level beneath the gates vertically to a level of the upper source/drain region.

Abstract: Semiconductor devices, having dual silicides, include a first fin, having N-type impurities, and a second fin, having P-type impurities, on a substrate. A first gate electrode and a first source/drain area are on the first fin. A second gate electrode and a second source/drain area are on the second fin. An etch stop layer is on the first source/drain area and the second source/drain area. An insulating layer is on the etch stop layer. A first plug connected to the first source/drain area and a second plug connected to the second source/drain area are formed through the insulating layer and the etch stop layer. A first metal silicide layer is in the first source/drain area. A second metal silicide layer having a material different from the first metal silicide layer and having a thickness smaller than the first metal silicide layer is in the second source/drain area.

Abstract: A method of forming a semiconductor structure of a control gate is provided, including depositing a first dielectric layer overlying a substrate, forming a surface modification layer from the first dielectric layer; and forming semiconductor dots on the surface modification layer. The surface modification layer has a bonding energy to the semiconductor dots less than the bonding energy between the first dielectric layer and the semiconductor dots. Therefore the semiconductor dots have higher density to form on the surface modification layer than that to directly form on the first dielectric layer. And a semiconductor device is also provided to tighten threshold voltage (Vt) and increase programming efficiency.

Abstract: Image sensors comprising an isolation region according to embodiments are disclosed, as well as methods of forming the image sensors with isolation region. An embodiment is a structure comprising a semiconductor substrate, a photo element in the semiconductor substrate, and an isolation region in the semiconductor substrate. The isolation region is proximate the photo element and comprises a dielectric material and an epitaxial region. The epitaxial region is disposed between the semiconductor substrate and the dielectric material.

Abstract: A semiconductor device may include pipe channel layer, and a pipe gate surrounding the pipe channel layer. The semiconductor device may include an oxidization layer formed between the pipe gate and the pipe channel layer. The semiconductor device may include a source side channel layer and a drain side channel layer extended from the pipe channel layer to protrude further than the oxidization layer.

Abstract: An upper planar capacitor is spaced above a lower planar capacitor by a dielectric layer. A bridged-post inter-layer connector couples the capacitances in parallel, through first posts and second posts. The first posts and second posts extend through the dielectric layer, adjacent the upper and lower planar capacitors. A first level coupler extends under the dielectric layer and couples the first posts together and to a conductor of the lower planar capacitor, and couples another conductor of the lower planar capacitor to one of the second posts. A second level coupler extends above the dielectric layer, and couples the second posts together and to a conductor of the upper planar capacitor, and couples another conductor of the upper planar capacitor to one of the first posts.

Abstract: A semiconductor device includes a substrate, a fin structure on the substrate, the fin structure comprising a doped region, a first gate over the fin structure, the first gate positioned adjacent the doped region, the first gate having a spacer on a first side and having no spacer on a second side between the gate and the doped region, and a conductive plug that contacts the doped region and a top of the gate.

Abstract: A quantum qubit coupling structure is provided. The quantum qubit coupling structure includes a plurality of qubits and a variable capacitor electrically connected between the plurality of qubits to vary coupling constants of the plurality of qubits.

Abstract: The present disclosure relates to an array substrate, a display panel and a display device. The array substrate includes a display area and a peripheral area surrounding the display area. The peripheral area includes a gate drive circuit which is electrically connected to a plurality of signal lines so as to provide the scanning signals to the display area. The display area includes a plurality of sub-pixels arranged in an array pattern and at least one wiring areas disposed between the sub-pixels, at least one signal line which is electrically connected to the gate drive circuit is provided in the at least one wiring areas.