Patents Examined by Wasiul Haider
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Patent number: 10381330Abstract: A method of bonding a first substrate to a second substrate, wherein the first substrate includes first electrical contacts on a top surface of the first substrate, and wherein the second substrate includes second electrical contacts on a bottom surface of the second substrate. The method includes forming a block of polyimide on the top surface of the first substrate, wherein the block of polyimide has a rounded upper corner, and vertically moving the top surface of the first substrate and the bottom surface of the second substrate toward each other until the first electrical contacts abut the second electrical contacts, wherein during the moving, the second substrate makes contact with the rounded upper corner of the polyimide causing the first and second substrates to move laterally relative to each other.Type: GrantFiled: March 14, 2018Date of Patent: August 13, 2019Assignee: Silicon Storage Technology, Inc.Inventors: Justin Hiroki Sato, Bomy Chen, Walter Lundy
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Patent number: 10373986Abstract: An array substrate, a display panel and a display device, including at least two gate lines in a display area, a gate driving circuit and at least two gate fan-out lines in a non-display are described. One end of each of the gate fan-out lines are electrically connected with one signal output of the gate driving circuit and the other end of each of the gate fan-out lines are electrically connected with the gate lines. By configuring a first gate fan-out line of the gate fan-out lines and the gate driving circuit to have an overlapping area outside a mutual connection area, an area where the gate fan-out lines are overlaps the gate driving circuit, space occupied by the first gate fan-out line outside the gate driving circuit is decreased to shorten a distance between the gate driving circuit and the display area.Type: GrantFiled: February 12, 2018Date of Patent: August 6, 2019Assignee: XIAMEN TIANMA MICRO-ELECTRONICS CO., LTD.Inventors: Guochang Lai, Junyi Li, Zhongjie Zhang
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Patent number: 10374012Abstract: Provided herein may be an electronic device including a semiconductor memory. The semiconductor memory may include: first column lines and sub-column lines extending in a first direction; first row lines extending in a second direction; first tiles including first memory cells connected between the first column lines and the first row lines; first contact plugs coupled to the sub-column lines and disposed between the first tiles in the first direction; second contact plugs coupled to the first row lines and disposed between the first tiles in the second direction; and a first connection structure partially coupling the first column lines to the sub-column lines such that the longer a current path on a first row line from a selected first memory cell to the corresponding second contact plug, the shorter a current path from the selected first memory cell to the corresponding first contact plug.Type: GrantFiled: July 9, 2018Date of Patent: August 6, 2019Assignee: SK HYNIX INC.Inventor: Dong Hoon Kim
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Patent number: 10354876Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate and a material layer. The substrate has a first region, and the material layer is disposed on the substrate. The material layer includes plural of first patterns and plural of second patterns arranged in an array, and two third patterns. The first patterns are disposed within the first region, the second patterns are disposed at two opposite outer sides of the first region, and the third patterns are disposed at another two opposite outer sides of the first region, wherein each of the third patterns partially merges each of a part of the first patterns and each of a part of the second patterns.Type: GrantFiled: June 24, 2018Date of Patent: July 16, 2019Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.Inventors: Feng-Yi Chang, Yu-Cheng Tung, Fu-Che Lee, Ying-Chih Lin
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Patent number: 10347599Abstract: A method of forming a semiconductor detector including: forming a p-n junction diode in an active device layer of a silicon-on-insulator (SOI) substrate, the active device layer being formed on an insulator layer of the SOI substrate; forming a first opening through the insulator layer to access a backside of a first doped region of the diode, the first doped region underlying a second doped region of the diode; forming a back contact on a back surface of the first doped region and electrically connecting with the first doped region; forming a conductive interconnect layer on an upper surface of the SOI substrate, the interconnect layer including a first top contact providing electrical connection with the second doped region; and forming an electrode in the first opening on the backside of the detector structure, the electrode providing electrical connection with the back contact of the diode.Type: GrantFiled: July 11, 2018Date of Patent: July 9, 2019Assignee: International Business Machines CorporationInventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
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Patent number: 10333033Abstract: A light emitting device according to an embodiment includes a body having a recess; a light emitting chip disposed in the recess; and a first dampproof layer sealing the light emitting chip and extended from a surface of the light emitting chip to a bottom of the recess, wherein the light emitting chip includes a wavelength range of 100 nm to 280 nm, and the first dampproof layer includes a fluororesin-based material.Type: GrantFiled: July 17, 2015Date of Patent: June 25, 2019Assignee: LG INNOTEK CO., LTD.Inventors: Jae Jin Kim, Do Hwan Kim
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Patent number: 10283463Abstract: A method of forming a semiconductor detector including: forming a p-n junction diode in an active device layer of a silicon-on-insulator (SOI) substrate, the active device layer being formed on an insulator layer of the SOI substrate; forming a first opening through the insulator layer to access a backside of a first doped region of the diode, the first doped region underlying a second doped region of the diode; forming a back contact on a back surface of the first doped region and electrically connecting with the first doped region; forming a conductive interconnect layer on an upper surface of the SOI substrate, the interconnect layer including a first top contact providing electrical connection with the second doped region; and forming an electrode in the first opening on the backside of the detector structure, the electrode providing electrical connection with the back contact of the diode.Type: GrantFiled: April 11, 2017Date of Patent: May 7, 2019Assignee: International Business Machines CorporationInventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi
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Patent number: 10269787Abstract: Methods for cutting (e.g., dividing) metal gate structures in semiconductor device structures are provided. A dual layer structure can form sub-metal gate structures in a replacement gate manufacturing processes, in some examples. In an example, a semiconductor device includes a plurality of metal gate structures disposed in an interlayer dielectric (ILD) layer disposed on a substrate, an isolation structure disposed between the metal gate structures, wherein the ILD layer circumscribes a perimeter of the isolation structure, and a dielectric structure disposed between the ILD layer and the isolation structure.Type: GrantFiled: November 10, 2017Date of Patent: April 23, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shiang-Bau Wang, Ming-Ching Chang, Shu-Yuan Ku, Ryan Chia-Jen Chen
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Patent number: 10256326Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.Type: GrantFiled: December 2, 2016Date of Patent: April 9, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Marc A. Bergendahl, Kangguo Cheng, Fee Li Lie, Eric R. Miller, Jeffrey C. Shearer, John R. Sporre, Sean Teehan
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Patent number: 10249628Abstract: A semiconductor device includes a device isolation region defining an active region in a substrate, and gate structures buried in the active region of the substrate. At least one of the gate structures includes a gate trench, a gate insulating layer conformally formed on an inner wall of the gate trench, a gate barrier pattern conformally formed on the gate insulating layer disposed on a lower portion of the gate trench, a gate electrode pattern formed on the gate barrier pattern and filling the lower portion of the gate trench, an electrode protection layer conformally formed on the gate insulating layer disposed on an upper portion of the gate trench to be in contact with the gate barrier pattern and the gate electrode pattern, a buffer oxide layer conformally formed on the electrode protection layer, and a gate capping insulating layer formed on the buffer oxide layer to fill the upper portion of the gate trench.Type: GrantFiled: January 9, 2018Date of Patent: April 2, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventor: Min-Hee Cho
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Patent number: 10249795Abstract: The invention provides an LED chip having an integrated electrostatic switch for electromechanical control of the LED. A suspended beam switch floats above a conductive control electrode, and by a charging of the electrode may be attracted downward to make connection between an LED structure and an external electrode. Components are mounted on a common substrate so that a fully integrated LED with MEMS switch is formed. Methods for producing the LED chip are further provided, in which production of the switching mechanism is fully integrated with the production of the LED structure.Type: GrantFiled: February 3, 2016Date of Patent: April 2, 2019Assignee: Koninklijke Philips N.V.Inventors: Peter Van Delft, Theodorus Johannes Petrus Van Den Biggelaar, Harald Josef Guenther Radermacher, Bob Bernardus Anthonius Theunissen
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Patent number: 10242975Abstract: A flexible display apparatus includes: a flexible substrate including a first surface and a second surface which is opposite to the first surface; a first display unit which displays an image with light and is on the first surface of the flexible substrate, the first display unit including a transmission area at which light from the flexible substrate passes through the first display unit to outside the first display unit; and a second display unit which displays an image with light and is on the second surface of the flexible substrate, the second display unit disposed corresponding to the transmission area of the first display unit on the first surface of the flexible substrate.Type: GrantFiled: April 11, 2017Date of Patent: March 26, 2019Assignee: SAMSUNG DISPLAY CO., LTD.Inventor: Mugyeom Kim
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Patent number: 10236428Abstract: A lead frame is disclosed. In an embodiment, the lead frame includes a frame having a plurality of lead frame sections, wherein the lead frame sections are connected to the frame, wherein the frame has at least two longitudinal sides and at least two transverse sides, wherein at least in one longitudinal side includes an imprint, and wherein the imprint bolsters stability of the longitudinal side against sagging.Type: GrantFiled: December 29, 2015Date of Patent: March 19, 2019Assignee: OSRAM Opto Semiconductors GmbHInventors: Weng Chung Tan, Rodello Cadiz Sigalat, Hussen Mohd Hanifah, Tobias Gebuhr
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Patent number: 10232471Abstract: The invention relates to a method for dividing a composite into a plurality of semiconductor chips along a dividing pattern. A composite, which comprises a substrate, a semiconductor layer sequence, and a functional layer, is provided. Separating trenches are formed in the substrate along the dividing pattern. The functional layer is cut through along the dividing pattern by means of coherent radiation. Each divided semiconductor chip has part of the semiconductor layer sequence, part of the substrate, and part of the functional layer. The invention further relates to a semiconductor chip.Type: GrantFiled: December 18, 2017Date of Patent: March 19, 2019Assignee: OSRAM OPTO SEMICONDUCTORS GMBHInventor: Mathias Kaempf
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Patent number: 10229902Abstract: Stack device having voltage compensation. In some embodiments, a switching device can include switching elements connected in series between a first terminal and a second terminal, with a first end switching element being connected to the first terminal and a second end switching element being connected to the second terminal. Each switching element can have a parameter such that the switching elements have a distribution of parameter values that decreases from the first end switching element for at least half of the switching elements to a minimum parameter value corresponding to a switching element between the first end switching element and the second end switching element. The minimum parameter value can be less than the parameter value of the second end switching element, and the parameter value of the first end switching element can be greater than or equal to the parameter value of the second end switching element.Type: GrantFiled: August 1, 2017Date of Patent: March 12, 2019Assignee: Skyworks Solutions, Inc.Inventors: Yu Zhu, David Scott Whitefield, Ambarish Roy, Guillaume Alexandre Blin
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Patent number: 10217684Abstract: A resin molding includes a semiconductor element, a circuit board, and a resin. A conductor connected to the semiconductor element is formed on the circuit board. The resin is adhered and integrated with the circuit board. A resin leakage suppression layer including a material having a higher thermal conductivity than that of a material forming a surface layer of the circuit board is provided in an edge region extending along a portion adhered to the resin in the circuit board and extending along at least one-side side surface of the resin.Type: GrantFiled: June 14, 2016Date of Patent: February 26, 2019Assignee: Hitachi Automotive Systems, Ltd.Inventors: Tsubasa Watanabe, Tsutomu Kono, Takayuki Yogo, Hiroaki Hoshika
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Patent number: 10211130Abstract: A semiconductor device includes a plurality of leads, a semiconductor element electrically connected to the leads and supported by one of the leads, and a sealing resin covering the semiconductor element and a part of each lead. The sealing resin includes a first edge, a second edge perpendicular to the first edge, and a center line parallel to the first edge. The reverse surfaces of the respective leads include parts exposed from the sealing resin, and the exposed parts include an outer reverse-surface mount portion and an inner reverse-surface mount portion that are disposed along the second edge of the sealing resin. The inner reverse-surface mount portion is closer to the center line of the sealing resin than is the outer reverse-surface mount portion. The outer reverse-surface mount portion is greater in area than the inner reverse-surface mount portion.Type: GrantFiled: January 26, 2017Date of Patent: February 19, 2019Assignee: ROHM CO., LTD.Inventor: Katsuhiro Iwai
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Patent number: 10205016Abstract: A method of forming an integrated circuit includes forming gate trenches in the first main surface of a semiconductor substrate, the gate trenches being formed so that a longitudinal axis of the gate trenches runs in a first direction parallel to the first main surface. The method further includes forming a source contact groove running in a second direction parallel to the first main surface, the second direction being perpendicular to the first direction, the source contact groove extending along the plurality of gate trenches, forming a source region including performing a doping process to introduce dopants through a sidewall of the source contact groove, and filling a sacrificial material in the source contact groove. The method also includes, thereafter, forming components of the logic circuit element, thereafter, removing the sacrificial material from the source contact groove, and filling a source conductive material in the source contact groove.Type: GrantFiled: April 11, 2017Date of Patent: February 12, 2019Assignee: Infineon Technologies AGInventors: Andreas Meiser, Till Schloesser, Detlef Weber, Karl-Heinz Gebhardt
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Patent number: 10197831Abstract: A flexible TFT backplane includes, a flexible substrate, a first set of address line contacts associated with the substrate, and a second set of address line contacts associated with the substrate. The first set of address line contacts and the second set of address line contacts are located at opposite sides of the substrate from each other, defining a vertical direction. A first set of address lines designed to run in one of the vertical direction and a diagonal or non-vertical direction with respect to the defined vertical direction, with the first set of address lines connected to the first set of address line contacts. Also provided is a second set of address lines designed to run in one of a diagonal or non-vertical direction with respect to the defined vertical direction, and a combination of diagonal and horizontal directions with respect to the vertical direction, with the second set of address lines connected to the second set of address line contacts.Type: GrantFiled: December 18, 2017Date of Patent: February 5, 2019Assignee: PALO ALTO RESEARCH CENTER INCORPORATEDInventors: Robert A. Street, Julie A. Bert, John C. Knights
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Patent number: 10186560Abstract: Provided are an organic light-emitting display apparatus and a method of manufacturing the same. The organic light-emitting display apparatus includes: a substrate on which a display area is defined, wherein an image is displayed on the display area; a thin film transistor arranged on the display area of the substrate; a via-insulating layer covering the thin film transistor; a pixel electrode arranged on the via-insulating layer and electrically connected to the thin film transistor; a pixel-defining layer including an opening exposing a central portion of the pixel electrode, and covering an edge of the pixel electrode; a counter electrode facing the pixel electrode; an organic emission layer arranged between the pixel electrode and the counter electrode; a wire arranged on the via-insulating layer to be spaced apart from the pixel electrode and including a spacer area and a non-spacer area; and a spacer arranged on the spacer area.Type: GrantFiled: March 3, 2017Date of Patent: January 22, 2019Assignee: Samsung Display Co., Ltd.Inventors: Jungkyu Lee, Taehyun Kim, Seungmin Lee, Sangho Park, Joosun Yoon