Abstract: The disclosure relates to methods of forming etch-resistant spacers in an integrated circuit (IC) structure. Methods according to the disclosure can include: forming a mask on an upper surface of a gate structure positioned over a substrate; forming a spacer material on the substrate, the mask, and exposed sidewalls of the gate structure; forming a separation layer over the substrate and laterally abutting the spacer material to a predetermined height, such that an exposed portion of the spacer material is positioned above an upper surface of the separation layer and at least partially in contact with the mask; and implanting a dopant into the exposed portion of the spacer material to yield a dopant-implanted region within the spacer material, wherein the dopant-implanted region of the spacer material has a greater etch resistivity than a remainder of the spacer material.

Abstract: Disclosed herein are methods for additive formation of a STT-MRAM metal stack using a deposition process through a pre-patterned template that skims away metal ions that are less likely to enable anisotropic deposition on a substrate. The pre-patterned template is formed from a film stack using patterning techniques to form an opening in the film stack that exposes portions of an underlying substrate where a MTJ will be formed for an MRAM cell. The film stack cavity may be exposed to etch processes that selectively pull back the sidewall, such that other layers in the film stack protrude into the cavity. Additional treatments to the other layers may alter the opening sizes in the other layers. Metal deposited through the cavity such that metal ions with anisotropic characteristics will be skimmed away before reaching the substrate.

Abstract: A structure having: a plurality of field effect transistors (FETs) connected between a common input and a common output, each one of the field effect transistors comprises: a source region, a drain region, and a gate electrode for controlling carriers through a channel region of a transistor region of the structure between the source region and the drain region; a plurality of diodes, each one of the diodes being associated with a corresponding one of the plurality of FETs, each one of the diodes having an electrode in Schottky contact with a diode region of the corresponding one of the FETs. The gate electrode and the diode electrode extend along parallel lines. The source region, the drain region, the channel region, and a diode region having therein the diode are disposed along a common line.

Abstract: A semiconductor device (1001) includes a thin-film transistor (101) including a gate electrode (3), an oxide semiconductor layer (7), a gate insulating layer (5), a source electrode (9s), and a drain electrode (9d); a metal oxide layer (8) including a conductor region (70c) and formed from an oxide film from which the oxide semiconductor layer (7) is also formed; an interlayer insulating layer (13) covering the thin-film transistor and the metal oxide layer (8); and a transparent conductive layer (15) disposed on the interlayer insulating layer and electrically connected to the drain electrode, wherein the oxide semiconductor layer (7) and the metal oxide layer (8) contain indium, tin, and zinc, and the transparent conductive layer (15) overlaps at least a portion of the conductor region (70c) with the interlayer insulating layer (13) therebetween.

Abstract: A method for fabricating a fully depleted silicon on insulator (FDSOI) device is described. A charge trapping layer in a buried oxide layer is provided on a semiconductor substrate. A backgate well in the semiconductor substrate is provided under the charge trapping layer. A device structure including a gate structure, source and drain regions is disposed over the buried oxide layer. A charge is trapped in the charge trapping layer. The threshold voltage of the device is partially established by the charge trapped in the charge trapping layer. Different aspects of the invention include the structure of the FDSOI device and a method of tuning the charge trapped in the charge trapping layer of the FDSOI device.

Abstract: A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.

Abstract: A non-volatile memory cell is disclosed. A select gate transistor, a following gate transistor, and an antifuse varactor are coupled in series on an active area. The following gate transistor is disposed between the select gate transistor and the antifuse varactor. A first ion well and a second ion well having the first conductivity type are provided in the active area. The following gate transistor partially overlaps with the first ion well. The second ion well has a doping concentration that is smaller than that of the first ion well.

Abstract: An imaging device which can perform imaging with a global shutter system and in which transistors are shared by pixels is provided. The imaging device includes first and second photoelectric conversion elements and first to sixth transistors. Active layers of the first to fourth transistors each include an oxide semiconductor. The imaging device has a configuration in which a reset transistor and an amplifier transistor are shared by a plurality of pixels and can perform imaging with a global shutter system. In addition, the imaging device can be used as a high-speed camera.

Abstract: A display device is provided including a display region arranged with a plurality of pixels, and a first sealing region arranged in an exterior periphery part of the display region, the display region includes an individual pixel electrode arranged in each of the plurality of pixels, a common pixel electrode arranged in upper layer of the individual pixel electrode and in succession to the plurality of pixels, and a light emitting layer arranged between the individual pixel electrode and the common pixel electrode, and the first sealing region includes a sealing layer arranged on a lower layer than the common pixel electrode and a region stacked with the common pixel electrode extending from the display region, the stacked region being enclosed by the display region.

Abstract: A method of fabricating a semiconductor device includes forming first and second fin patterns in an active region and in a measurement region of a substrate, respectively, the measurement region being different from the active region, forming first and second gate electrodes to cross the first and second fin patterns, respectively, and measuring a contact potential difference (Vcpd) of the second gate electrode to determine a threshold voltage of the first gate electrode based on the measured contact potential difference (Vcpd).

Abstract: A semiconductor device comprises a nanowire arranged over a substrate, a gate stack arranged around the nanowire, a spacer arranged along a sidewall of the gate stack, a cavity defined by a distal end of the nanowire and the spacer, and a source/drain region partially disposed in the cavity and in contact with the distal end of the nanowire.

Abstract: A semiconductor device includes a first well and a second well provided within a semiconductor substrate, an isolation region disposed between the first well and the second well within the semiconductor substrate, a first wiring disposed on the first well, a second wiring disposed on the second well, a concave third wiring disposed on the isolation region, a buried insulating film disposed on the third wiring so as to fill the concave portion thereof, a plurality of fourth wirings disposed on the buried insulating film, and a contact plug disposed so as to electrically connect to at least one of the first and second wells.

Abstract: Embodiments of the present disclosure include semiconductor packages and methods of forming the same. An embodiment is a semiconductor package including a first package including one or more dies, and a redistribution layer coupled to the one or more dies at a first side of the first package with a first set of bonding joints. The redistribution layer including more than one metal layer disposed in more than one passivation layer, the first set of bonding joints being directly coupled to at least one of the one or more metal layers, and a first set of connectors coupled to a second side of the redistribution layer, the second side being opposite the first side.

Abstract: The present disclosure provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, a first III-V compound layer over the substrate, a second III-V compound layer on the first III-V compound layer, a third III-V compound layer on the second III-V compound layer, a source region on the third III-V compound layer, and a drain region on the third III-V compound layer. A percentage of aluminum of the third III-V compound layer is greater than that of the second III-V compound layer.

Abstract: Some embodiments of the present disclosure relate to an integrated chip having a vertical transistor device. The integrated chip may have a semiconductor body with a trench extending along first sides of a source region, a channel region over the source region, and a drain region over the channel region. A gate electrode is arranged along a first sidewall of the trench, and a metal contact is arranged on the drain region. An isolation dielectric material is disposed within the trench. The isolation dielectric material is vertically over a top surface of the gate electrode and is laterally adjacent to the gate electrode.

Abstract: A semiconductor device includes a semiconductor substrate, a photoelectric conversion element, a first isolation insulating film, and a current blocking region. The first isolation insulating film is formed around the photoelectric conversion element. The current blocking region is formed in a region between the photoelectric conversion element and the first isolation insulating film. The current blocking region includes an impurity diffusion layer, and a defect extension preventing layer disposed in contact with the impurity diffusion layer to form a twin with the impurity diffusion layer. The defect extension preventing layer has a different crystal structure from that of the impurity diffusion layer. At least a part of the current blocking region is disposed in contact with the first isolation insulating film.

Abstract: Disclosed herein are methods of forming non-volatile storage. An opening may be etched through a stack of two alternating materials to a semiconductor substrate. A silicon nitride film may be formed on a vertical sidewall of the opening. The semiconductor substrate may be cleaned to remove oxide from the semiconductor substrate. The silicon nitride film protects the materials in the stack while cleaning the semiconductor substrate. The silicon nitride film may be converted to an oxide after cleaning the semiconductor substrate. A semiconductor region may be formed in contact with the cleaned semiconductor substrate. A memory cell film may be formed over the oxide in the opening. Control gates may be formed by replacing one of the materials in the stack with a conductive material. The oxide may serve as a blocking layer between the control gates and charge storage regions in the memory cell film.

Abstract: This hetero-junction bipolar transistor includes a first n-type GaN layer, an AlxGa1-xN layer (0.1?x?0.5), an undoped GaN layer having a thickness of not less than 20 nm, a Mg-doped p-type GaN layer having a thickness of not less than 100 nm, and a second n-type GaN layer which are sequentially stacked. The first n-type GaN layer and the AlxGa1-xN layer form an emitter, the undoped GaN layer and the p-type GaN layer form a base, and the second n-type GaN layer forms a collector. During non-operation, two-dimensional hole gas is formed in a part of the undoped GaN layer near the hetero interface between the AlxGa1-xN layer and the undoped GaN layer. When the thickness of the p-type GaN layer is b [nm], the hole concentration of the p-type GaN layer is p [cm?3], and the concentration of the two-dimensional hole gas is Ps [cm?2], p×b×10?7+Ps?1×1013 [cm?2] is satisfied.

Abstract: Disclosed is a semiconductor light emitting device, including: a body, which has a bottom part with at least one hole formed therein, a side wall, and a cavity defined by the bottom part and the side wall; a semiconductor light emitting chip, which is placed in each hole and includes plural semiconductor layers adapted to generate light by electron-hole recombination and electrodes electrically connected to the plural semiconductor layers; and an encapsulating member provided at least to the cavity to cover the semiconductor light emitting chip, in which the electrodes of the semiconductor light emitting chip are exposed towards the lower face of the bottom part of the body.

Abstract: The present invention relates to a method of manufacturing a capacitive micro-machined transducer (100), in particular a CMUT, the method comprising depositing a first electrode layer (10) on a substrate (1), depositing a first dielectric film (20) on the first electrode layer (10), depositing a sacrificial layer (30) on the first dielectric film (20), the sacrificial layer (30) being removable for forming a cavity (35) of the transducer, depositing a second dielectric film (40) on the sacrificial layer (30), and depositing a second electrode layer (50) on the second dielectric film (40), wherein the first dielectric film (20) and/or the second dielectric film (40) comprises a first layer comprising an oxide, a second layer comprising a high-k material, and a third layer comprising an oxide, and wherein the depositing steps are performed by Atomic Layer Deposition. The present invention further relates to a capacitive micro-machined transducer (100), in particular a CMUT, manufactured by such method.