Abstract: A flexible TFT backplane includes, a flexible substrate, a first set of address line contacts associated with the substrate, and a second set of address line contacts associated with the substrate. The first set of address line contacts and the second set of address line contacts are located at opposite sides of the substrate from each other, defining a vertical direction. A first set of address lines designed to run in one of the vertical direction and a diagonal or non-vertical direction with respect to the defined vertical direction, with the first set of address lines connected to the first set of address line contacts. Also provided is a second set of address lines designed to run in one of a diagonal or non-vertical direction with respect to the defined vertical direction, and a combination of diagonal and horizontal directions with respect to the vertical direction, with the second set of address lines connected to the second set of address line contacts.

Abstract: Provided are an organic light-emitting display apparatus and a method of manufacturing the same. The organic light-emitting display apparatus includes: a substrate on which a display area is defined, wherein an image is displayed on the display area; a thin film transistor arranged on the display area of the substrate; a via-insulating layer covering the thin film transistor; a pixel electrode arranged on the via-insulating layer and electrically connected to the thin film transistor; a pixel-defining layer including an opening exposing a central portion of the pixel electrode, and covering an edge of the pixel electrode; a counter electrode facing the pixel electrode; an organic emission layer arranged between the pixel electrode and the counter electrode; a wire arranged on the via-insulating layer to be spaced apart from the pixel electrode and including a spacer area and a non-spacer area; and a spacer arranged on the spacer area.

Abstract: An image sensor includes a semiconductor substrate and a photoelectric conversion device on the semiconductor substrate and including a plurality of pixel electrodes, a light absorption layer, and a common electrode. The plurality of pixel electrodes may include a first pixel electrode and a second pixel electrode. The photoelectric conversion device may include a first photoelectric conversion region defined in an overlapping region with the first pixel electrode, the light absorption layer, and the common electrode, and a second photoelectric conversion region defined in an overlapping region with the second pixel electrode, the light absorption layer, and the common electrode. Sensitivity of the first photoelectric conversion region may be higher than sensitivity of the second photoelectric conversion region. An electronic device may include the image sensor.

Abstract: A semiconductor device includes a first trench and a second trench, a liner pattern along a portion of side surfaces and along bottom surfaces of the first and the second trenches, respectively, a work function metal in the first and the second trenches and on the liner pattern, respectively, a first barrier metal in the first trench and on the work function metal, and having a first thickness, a second barrier metal in the second trench and on the work function metal, and having a second thickness thicker than the first thickness, and a first fill metal on the first barrier metal.

Abstract: A method for fabricating an advanced metal conductor structure is described. A pattern in a dielectric layer is provided. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is created over the patterned dielectric. A ruthenium layer is deposited over the adhesion promoting layer. Using a physical vapor deposition process, a cobalt layer is deposited over the ruthenium layer. A thermal anneal is performed which reflows the cobalt layer to fill the set of features to form a set of metal conductor structures.

Abstract: Fabricating a negative capacitance steep-switch transistor includes receiving a semiconductor structure including a substrate, a fin, a source/drain, a gate, a cap disposed upon the gate, a trench contact disposed upon the source/drain, and an inter-layer dielectric. A source/drain recess is formed in the inter-layer dielectric extending to the trench contact, and a gate recess is formed in the inter-layer dielectric extending to the gate. A ferroelectric material is deposited within the gate recess, and a source/drain contact is formed within the source/drain recess. A gate contact is formed within the gate recess, and a contact recess is formed in a portion of the source/drain contact. A bi-stable resistive system (BRS) material is formed in the contact recess, and a metallization layer contact is formed upon the BRS material. A portion of the source/drain contact, the BRS material, and a portion of the metallization layer contact forms a reversible switch.

Abstract: A semiconductor structure is provided that includes a bulk semiconductor substrate of a first semiconductor material. The structure further includes a plurality of fin pedestal structures of a second semiconductor material located on the bulk semiconductor substrate of the first semiconductor material, wherein the second semiconductor material is different from the first semiconductor material. In accordance with the present application, each fin pedestal structure includes a pair of spaced apart semiconductor fins of the second semiconductor material.

Abstract: A method for fabricating an advanced metal conductor structure is described. A pattern in a dielectric layer is provided. The pattern includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is created over the patterned dielectric. A ruthenium layer is deposited over the adhesion promoting layer. Using a physical vapor deposition process, a cobalt layer is deposited over the ruthenium layer. A thermal anneal is performed which reflows the cobalt layer to fill the set of features to form a set of metal conductor structures.

Abstract: An integrated circuit device has a substrate including a dielectric layer patterned with a pattern which includes a set of features in the dielectric for a set of metal conductor structures. An adhesion promoting layer is disposed on the set of features in the patterned dielectric. A ruthenium layer is disposed on the adhesion promoting layer. A cobalt layer is disposed on the ruthenium layer filling a first portion of the set of features. The cobalt layer has a u-shaped cross section having a thicker bottom layer than side layers. The cobalt layer is formed using a physical vapor deposition process. A metal layer is disposed on the cobalt layer filling a second, remainder portion of the set of features.

Abstract: An optical transducer, optoelectronic device, and semiconductor are disclosed. An illustrative optical transducer is disclosed to include a plurality of p-n stacks, where each p-n stack comprises at least a p-layer and an n-layer, and formed therein a built-in photovoltage between the p-layer and the n-layer. The p-layers and n-layers are disclosed to have substantially the same n-type material in substantially the same composition such that each p-n stack in the plurality of p-n stacks has a substantially similar built-in photovoltage. The optical transducer is further disclosed to include a plurality of connecting layers, each connecting layer in the plurality of connecting layers being sandwiched between two adjacent p-n stacks for electrically connecting the two adjacent p-n stacks. The p-n stacks in the plurality of p-n stacks may be arranged such that the built-in photovoltage of each p-n stack additively contributes to an overall electric potential of the transducer.

Abstract: Embodiments of mechanisms for forming dislocations in source and drain regions of finFET devices are provided. The mechanisms involve recessing fins and removing the dielectric material in the isolation structures neighboring fins to increase epitaxial regions for dislocation formation. The mechanisms also involve performing a pre-amorphous implantation (PAI) process either before or after the epitaxial growth in the recessed source and drain regions. An anneal process after the PAI process enables consistent growth of the dislocations in the source and drain regions. The dislocations in the source and drain regions (or stressor regions) can form consistently to produce targeted strain in the source and drain regions to improve carrier mobility and device performance for NMOS devices.

Abstract: An optoelectronic device with a multi-layer contact is described. The optoelectronic device can include a n-type semiconductor layer having a surface. A mesa can be located over a first portion of the surface of the n-type semiconductor layer and have a mesa boundary. A n-type contact region can be located over a second portion of the surface of the n-type semiconductor contact layer entirely distinct from the first portion, and be at least partially defined by the mesa boundary. A first n-type metallic contact layer can be located over at least a portion of the n-type contact region in proximity of the mesa boundary, where the first n-type metallic contact layer forms an ohmic contact with the n-type semiconductor layer. A second n-type metallic contact layer can be located over a second portion of the n-type contact region, where the second n-type metallic contact layer is formed of a reflective metallic material.

Abstract: A semiconductor structure includes a HV NMOS structure. The HV NMOS structure includes a source region, a drain region, a channel region, a gate dielectric, and a gate electrode. The source region and the drain region are separated from each other. The channel region is disposed between the source region and the drain region. The channel region has a channel direction from the source region toward the drain region. The gate dielectric is disposed on the channel region and on portions of the source region and the drain region. The gate electrode is disposed on the gate dielectric. The gate electrode includes a first portion of n-type doping and two second portions of p-type doping. The two second portions are disposed at two sides of the first portion. The two second portions have an extending direction perpendicular to the channel direction.

Abstract: Integrated circuit structures and methods for forming the same are provided. An integrated circuit includes a dielectric layer in a memory region and a logic region. The integrated circuit structure also includes a first conductive feature in the dielectric layer in the memory region. The integrated circuit structure further includes a second conductive feature in the dielectric layer in the logic region. In addition, the integrated circuit structure includes an active memory cell over the dielectric layer in the memory region. The active memory cell is connected to the first conductive feature. The integrated circuit structure also includes a dummy memory cell over the dielectric layer in the logic region. The dummy memory cell is connected to the second conductive feature.

Abstract: Disclosed is a wafer or a material stack for semiconductor-based optoelectronic or electronic devices that minimizes or reduces misfit dislocation, as well as a method of manufacturing such wafer of material stack. A material stack according to the disclosed technology includes a substrate; a basis buffer layer of a first material disposed above the substrate; and a plurality of composite buffer layers disposed above the basis buffer layer sequentially along a growth direction. The growth direction is from the substrate to a last composite buffer layer of the plurality of composite buffer layers. Each composite buffer layer except the last composite buffer layer includes a first buffer sublayer of the first material, and a second buffer sublayer of a second material disposed above the first buffer sublayer. The thicknesses of the first buffer sublayers of the composite buffer layers decrease along the growth direction.

Abstract: A magnetic solid state device is disclosed. The magnetic solid state device includes a substrate and a topological insulator deposited on top of the substrate. The magnetic solid state device also includes a first perpendicular magnetic anisotropy (PMA) bit having a reference PMA layer located on the topological insulator, and a second PMA bit having a free PMA layer located on the topological insulator. A gate contact is utilized to receive various predetermined voltages for controlling the Ruderman-Kittel-Kasuya-Yosida (RKKY) interactions between the reference PMA layer in the first PMA bit and the free PMA layer in the second PMA bit.

Abstract: The present invention provides a method of manufacturing a semiconductor device to improve the manufacturing yield of the semiconductor device. The manufacturing method includes the steps of: forming a groove extending in a first direction (y direction) across a first power transistor formation region and a second power transistor formation region, in a back surface of a semiconductor wafer; filling the groove with a conductor film by forming the conductor film on the back surface in which the groove is formed; and exposing the back surface of the semiconductor wafer by removing a portion of the conductor film.

Abstract: A method for manufacturing an SOI wafer having SOI layer includes a thinning step to adjust SOI film thickness of the SOI wafer, including the steps of: (A1) measuring the SOI film thickness of the SOI wafer having the SOI layer before the thinning step; (A2) determining rotational position of the SOI wafer in the thinning step on the basis of a radial SOI film thickness distribution obtained in the measuring of the film thickness and previously determined radial stock removal distribution in the thinning step, and rotating the SOI wafer around the central axis thereof so as to bring the SOI wafer to the determined rotational position; and (A3) thinning the SOI layer of the rotated SOI wafer. The method for manufacturing the SOI wafer can produce an SOI wafer with an excellent radial film thickness uniformity of the SOI layer after the thinning step.

Abstract: The disclosure relates to methods of forming etch-resistant spacers in an integrated circuit (IC) structure. Methods according to the disclosure can include: forming a mask on an upper surface of a gate structure positioned over a substrate; forming a spacer material on the substrate, the mask, and exposed sidewalls of the gate structure; forming a separation layer over the substrate and laterally abutting the spacer material to a predetermined height, such that an exposed portion of the spacer material is positioned above an upper surface of the separation layer and at least partially in contact with the mask; and implanting a dopant into the exposed portion of the spacer material to yield a dopant-implanted region within the spacer material, wherein the dopant-implanted region of the spacer material has a greater etch resistivity than a remainder of the spacer material.

Abstract: Disclosed herein are methods for additive formation of a STT-MRAM metal stack using a deposition process through a pre-patterned template that skims away metal ions that are less likely to enable anisotropic deposition on a substrate. The pre-patterned template is formed from a film stack using patterning techniques to form an opening in the film stack that exposes portions of an underlying substrate where a MTJ will be formed for an MRAM cell. The film stack cavity may be exposed to etch processes that selectively pull back the sidewall, such that other layers in the film stack protrude into the cavity. Additional treatments to the other layers may alter the opening sizes in the other layers. Metal deposited through the cavity such that metal ions with anisotropic characteristics will be skimmed away before reaching the substrate.