Abstract: A memory device includes a capacitor, a tunneling-enhanced device, and a transistor. In accordance with an embodiment, capacitor has first and second electrodes wherein the first electrode of the capacitor serves as a control gate of the memory device. The tunneling-enhanced device has a first electrode and a second electrode, wherein the first electrode of the second capacitor serves as an erase gate of the memory device and the second electrode of the tunneling-enhanced device is coupled to the second electrode of the capacitor to form a floating gate. The transistor has a control electrode and a pair of current carrying electrodes, wherein the control electrode of the transistor is directly coupled to the floating gate. In accordance with another embodiment, a method for manufacturing the memory device includes a method for manufacturing the memory device.

Abstract: Luminaires and luminaire components are provided that may include emissive, index-matching, and/or outcoupling components that are replaceable separately from other components of the luminaire. In some embodiments, an index-matching component may include a gel sheet or pad that can be disposed between an emissive component and an outcoupling component. The index-matching component may be replaceable separately from the emissive and outcoupling components. In some embodiments, an emissive component including an OLED panel and/or an index-matching component may be replaceable separately from other components of the luminaire.

Abstract: A semiconductor structure and a method for forming the same are provided. The method comprises: providing a first semiconductor workpiece; bonding a second semiconductor workpiece to a first surface of the first semiconductor workpiece; forming a first electrically conductive via through the second semiconductor workpiece to the first semiconductor workpiece; bonding a third semiconductor workpiece to a second surface of the first semiconductor workpiece, the second surface being opposite to the first surface; and forming a second electrically conductive via through the first semiconductor workpiece and the third semiconductor workpiece to the second semiconductor workpiece such that the first electrically conductive via and the second electrically conductive via are electrically connected.

Abstract: A wiring board includes a wiring layer including a surface on which a recess is formed and a metal layer formed on a bottom surface of the recess. A surface of the metal layer facing away from the bottom surface of the recess is closer to the bottom surface of the recess than is the surface of the wiring layer.

Abstract: Wafer bonding edge protection techniques are provided. In one aspect, a method of forming Cu interconnects in a wafer includes: forming a dielectric layer on the wafer; forming a first mask on the dielectric layer; patterning the first mask with a footprint/location of the Cu interconnects, wherein the patterning of the first mask is performed over an entire surface of the wafer; forming a second mask on the first mask, wherein the second mask covers a portion of the patterned first mask at an edge region of the wafer; patterning trenches in the dielectric layer through the first mask and the second mask, wherein the second mask blocks formation of the trenches at the edge region of the wafer and thereby provides edge protection during patterning of the trenches; and forming the Cu interconnects in the trenches. A wafer bonding method and interconnect structure are also provided.

Abstract: A package and a light emitting device with which production of burrs can be suppressed, and methods of manufacturing the package and the light emitting device easily are provided. A package includes a pair of lead electrodes made of metal plates and a resin molded body. A recess portion for mounting a light emitting element is formed. The pair of lead electrodes are exposed on a bottom surface of the recess portion. At least one of the pair of lead electrodes includes a groove portion that is formed on the metal plate and along a periphery of a surface of the metal plate exposed on a bottom surface of the recess portion.

Abstract: A method for forming a non-volatile memory device includes disposing a junction layer comprising a doped silicon-bearing material in electrical contact with a first conductive material, forming a switching layer comprising an undoped amorphous silicon-bearing material upon at least a portion of the junction layer, disposing a layer comprising a non-noble metal material upon at least a portion of the switching layer, disposing an active metal layer comprising a noble metal material upon at least a portion of the layer, and forming a second conductive material in electrical contact with the active metal layer.

Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a thin film containing a predetermined element, boron, carbon, and nitrogen on a substrate by performing a cycle a predetermined number of times. The cycle includes forming a first layer containing boron and a halogen group by supplying a first precursor gas containing boron and the halogen group to the substrate; and forming a second layer containing the predetermined element, boron, carbon, and nitrogen by supplying a second precursor gas containing the predetermined element and an amino group to the substrate and modifying the first layer.

Abstract: Various embodiments comprise apparatuses and methods including a memory array having alternating levels of semiconductor materials and dielectric material with strings of memory cells formed on the alternating levels. One such apparatus includes a memory array formed substantially within a cavity of a substrate. Peripheral circuitry can be formed adjacent to a surface of the substrate and adjacent to the memory array. Additional apparatuses and methods are described.

Abstract: Embodiments of semiconductor devices and methods of their formation include providing a semiconductor substrate having a top surface, a bottom surface, an active region, and an edge region, and forming a gate structure in a first trench in the active region of the semiconductor substrate. A termination structure is formed in a second trench in the edge region of the semiconductor substrate. The termination structure has an active region facing side and a device perimeter facing side. The method further includes forming first and second source regions of the first conductivity type are formed in the semiconductor substrate adjacent both sides of the gate structure. A third source region is formed in the semiconductor substrate adjacent the active region facing side of the termination structure. The semiconductor device may be a trench metal oxide semiconductor device, for example.

Abstract: Recrystallization and grain growth of an interconnect metal, such as Cu, is achieved at higher anneal temperatures of 150° C. to 600° C., for example, for short anneal times of five to 180 minutes by forming a metal stress locking layer on the interconnect metal before anneal and chemical-mechanical polishing. The stress locking layer extends the elastic region of the interconnect metal by suppressing atom diffusion to the free surface, resulting in near zero tensile stress at room temperature after anneal. Stress voiding, which creates reliability problems, is thereby avoided. Improved grain size and texture are also achieved. The stress locking layer is removed after anneal by chemical-mechanical polishing or wet etching leaving the metal interconnect with low stress and improved grain size and texture. Annealing can be done in a forming gas or nitrogen gas atmosphere.

Abstract: Described herein is a semiconductor device including a semiconductor substrate in which an element region and a termination region surrounding the element region are provided. The element region includes: a gate trench; a gate insulating film; and a gate electrode. The termination region includes: a plurality of termination trenches provided around the element region; an inner trench insulating layer located inside of each of the plurality of termination trenches; and an upper surface insulating layer located at an upper surface of the semiconductor substrate in the termination region. The upper surface insulating layer includes a first portion and a second portion having a thinner thickness than the first portion and located at a location separated from the element region than the first portion, and a gate wiring is located at an upper surface of the first portion and is not located at an upper surface of the second portion.

Abstract: The disclosure relates to semiconductor structures and, more particularly, to one or more devices with an engineered layer for modulating voltage threshold (Vt) and methods of manufacture. The method includes finding correlation of thickness of a buffer layer to out-diffusion of dopant into extension regions during annealing of a doped layer formed on the buffer layer. The method further includes determining a predetermined thickness of the buffer layer to adjust device performance characteristics based on the correlation of thickness of the buffer layer to the out-diffusion. The method further includes forming the buffer layer adjacent to gate structures to the predetermined thickness.

Abstract: In a method for manufacturing a semiconductor device, a first dielectric layer is formed over a substrate. A first set of recesses is formed in the first dielectric layer. A metal layer is formed in the first set of recesses. A set of metal wirings is formed from the metal layer in the first set of recesses. A second set of recesses is formed in the first dielectric layer. A second dielectric layer is formed over the set of metal wirings and in the second set of recesses. A third set of recesses is formed in the first dielectric layer and the second dielectric layer. A third dielectric layer is formed over the metal wirings and in the third set of recesses.

Abstract: A fin field effect transistor (finFET) and a method of fabricating the finFET. The method includes forming one or more fins above a substrate in a channel region, depositing a first insulating material conformally on the one or more fins and the substrate, and depositing a second insulating material over the first insulating material in non-channel regions adjacent to the channel region. A selective etch of the first insulating material in the channel region is performed to form a trench. The trench is filled with the second insulating material. The second insulating material in the channel region is adjacent to the first insulating material in the non-channel regions.

Abstract: A method of forming conductive vias comprises forming a first via opening and a second via opening within a substrate. First conductive material of a first conductivity is formed into the first and second via openings. The first conductive material lines sidewalls and a base of the second via opening to less-than-fill the second via opening. Second conductive material is formed into the second via opening over the first conductive material in the second via opening. The second conductive material is of a second conductivity that is greater than the first conductivity. All conductive material within the first via opening forms a first conductive via defining a first maximum conductance elevationally through the first conductive via and all conductive material within the second via opening forms a second conductive via defining a second maximum conductance elevationally through the second conductive via that is greater than said first maximum conductance.

Abstract: An embodiment isolation structure includes a first passivation layer over a bottom surface and extending along sidewalls of a trench in a semiconductor substrate, wherein the first passivation layer includes a first dielectric material. The semiconductor device further includes a passivation oxide layer in the trench on the first passivation layer, wherein the passivation oxide layer includes an oxide of the first dielectric material and has a higher atomic percentage of oxygen than the first passivation layer, The semiconductor device further includes a second passivation layer in the trench on the passivation oxide layer, wherein the second passivation layer also includes the first dielectric material and has a lower atomic percentage of oxygen than the passivation oxide layer.

Abstract: High voltage devices and methods for forming a high voltage device are disclosed. The method includes providing a substrate having top and bottom surfaces. The substrate is defined with a device region and a recessed region disposed within the device region. The recessed region includes a recessed surface disposed lower than the top surface of the substrate. A transistor is formed over the substrate. Forming the transistor includes forming a gate at least over the recessed surface and forming a source region adjacent to a first side of the gate below the recessed surface. Forming the transistor also includes forming a drain region displaced away from a second side of the gate. First and second device wells are formed in the substrate within the device region. The first device well encompasses the drain region and the second device well encompasses the source region.

Abstract: Provided is a method for a light conversion member including forming a plurality of grooves etched by a predetermined depth from a top surface to a bottom surface of a first substrate, forming a plurality of first connection members disposed in a first unit area partitioned by each of the grooves and having a closed loop shape surrounding each of the grooves on the top surface of the first substrate, forming a quantum dot member in the groove, forming a plurality of second connection members disposed in each of second unit areas partitioned on a bottom surface of a second substrate, cutting the second substrate along boundaries of the second unit areas; bonding a plurality of second sub substrates cut along the second unit areas to the top surface of the first substrate so as to overlap the first unit areas.

Abstract: A microelectronic device includes semiconductor device with a component at a front surface of the semiconductor device and a backside heat spreader layer on a back surface of the semiconductor device. The backside heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.