Abstract: A method of producing an optoelectronic component includes providing a lead frame subdivided by a separating region into first and second lead frame parts, carrying out etching in which at least one trench structure is produced on the upper side of the first lead frame, producing a molded body by molding a molding material around the lead frame such that 1) a cavity is formed and exposes a region of the upper side of the first lead frame part and a region of the upper side of the second lead frame part, and 2) the trench structure is provided on the upper side of the exposed region of the first lead frame part, and arranging the optoelectronic semiconductor chip on the upper side of the exposed region of the first lead frame part such that the trench structure is used as an alignment mark.

Abstract: A method for depositing a silicon-containing film is performed by causing a silicon-containing gas to adsorb on a first surface of a depression formed in a second surface of a substrate by supplying the silicon-containing gas to the substrate. A silicon component contained in the silicon-containing gas adsorbed on the first surface of the depression is partially etched by supplying an etching gas to the substrate. A silicon-containing film is deposited in the depression by supplying a reaction gas reactable with the silicon component to the substrate so as to produce a reaction product by causing the reaction gas to react with the silicon component left in the depression without being etched.

Abstract: There is provided a method of forming a nitride film, including: repeating a cycle including an adsorption process of adsorbing a film forming precursor gas onto a substrate having a surface in which a fine recess is formed, the film forming precursor gas containing an element and chlorine constituting a nitride film to be formed; and a nitriding process of nitriding the adsorbed film forming precursor gas with nitriding active species, to form the nitride film in the fine recess. The nitriding process includes: generating NH* active species and N* active species as a nitriding active species; and controlling concentrations of the NH* active species and the N* active species to vary an area where the film forming precursor gas is adsorbed in the fine recess.

Abstract: Methodologies and a device for SRAM patterning are provided. Embodiments include forming a spacer layer over a fin channel, the fin channel being formed in four different device regions; forming a bottom mandrel over the spacer layer; forming a top mandrel directly over the bottom mandrel, wherein the top and bottom mandrels including different materials; forming a buffer oxide layer over the top mandrel; forming an anti-reflective coating (ARC) over the first OPL; forming a photoresist (PR) over the ARC and patterning the PR; and etching the first OPL, ARC, buffer oxide, and top mandrel with the pattern of the PR, wherein a pitch of the PR as patterned is different in each of the four device regions.

Abstract: A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a top surface of a substrate, semiconductor local bit lines extending perpendicular to the top surface of the substrate, and resistivity switching memory elements located at each overlap region between the electrically conductive layers and the semiconductor local bit lines. Each of the semiconductor local bit lines includes a plurality of drain regions located at each level of the electrically conductive layers, and having a doping of a first conductivity type, and a semiconductor channel vertically extending from a level of a bottommost electrically conductive layer within the alternating stack to a level of a topmost electrically conductive layer within the alternating stack, and contacting the plurality of drain regions within the semiconductor local bit line.

Abstract: Under one aspect, a power Schottky diode includes a cathode; a semiconductor disposed over the cathode, the semiconductor including at least a first region and a second region, the second region defining a guard ring; an anode disposed over the first region and at least a portion of the guard ring, the anode including a metal, a junction between the anode and the first region defining a Schottky barrier; and an oxide disposed over the guard ring. Additionally, the power Schottky diode can include a resistive material disposed over at least a portion of the guard ring and at least a portion of the oxide. The resistive material can inhibit a flow of holes from the guard ring to the anode following a heavy ion strike to the guard ring. The anode further can be disposed over at least a portion of, or the entirety of, the resistive material.

Abstract: A semiconductor device includes a first semiconductor layer; an insulation member layer formed on the first semiconductor layer; a transistor disposed in an upper portion of the insulation member layer; a first interlayer insulation film covering the transistor; a layered member including a wiring layer formed on the first interlayer insulation film and a second interlayer insulation film; and a first penetrating electrode penetrating through the insulation member layer, the first interlayer insulation film, and the layered member. The first penetrating electrode is electrically connected only to the first semiconductor layer.

Abstract: An optoelectronic component includes a housing including a plastic material and a first lead frame section at least partly embedded in the plastic material, a first recess and a second recess, wherein a first upper section of an upper side of the first lead frame section is not covered by the plastic material in the first recess, a second upper section of the upper side of the first lead frame section is not covered by the plastic material in the second recess, the first recess and the second recess are separated from one another by a section of the plastic material, an optoelectronic semiconductor chip is arranged in the first recess, and no optoelectronic semiconductor chips is arranged in the second recess.

Abstract: A transistor has a substrate, source and drain electrodes on the substrate, the source and drain electrodes formed of a conductor ink having silver nanoparticles with integrated dipolar surfactants, an organic semiconductor forming a channel between the source and drain electrodes, the organic semiconductor in contact with the source and drain electrodes, a gate dielectric layer having a first surface in contact with the organic semiconductor, and a gate electrode in contact with a second surface of the gate dielectric layer, the gate electrode formed of silver nanoparticles with integrated dipolar surfactants.

Abstract: A method for forming a multilayer barrier comprises forming a conductive line over a substrate, depositing a dielectric layer over the conductive line, forming a plug opening in the dielectric layer, forming a multilayer barrier through a plurality of deposition processes and corresponding plasma treatment processes.

Abstract: A method of fabricating a solid state radiation detector method includes mechanically lapping and polishing the first and the second surfaces of a semiconductor wafer using a plurality of lapping and polishing steps. The method also includes growing passivation oxide layers by use of oxygen plasma on the top of the polished first and second surfaces in order to passivate the semiconductor wafer. Anode contacts are deposited and patterned on top of the first passivation oxide layer, which is on top of the first surface. Cathode contacts, which are either monolithic or patterned, are deposited on top of the second passivation oxide layer, which is on the second surface. Aluminum nitride encapsulation layer can be deposited over the anode contacts and patterned to encapsulate the first passivation oxide layer, while physically exposing a center portion of each anode contact to electrically connect the anode contacts.

Abstract: A semiconductor device includes a buried epitaxially grown substrate and a silicon on insulator (SOI) layer. The device also includes a buried oxide (BOX) layer between the buried epitaxially grown substrate and the SOI layer, an isolation trench having first width (w1), a contact trench having a second width (w2) and a capacitive trench having a third width (w3). Methods are described that allow the formation of the trenches in a normal process flow.

Abstract: Disclosed herein are methods for fabricating an organic photovoltaic device comprising depositing an amorphous organic layer and a crystalline organic layer over a first electrode, wherein the amorphous organic layer and the crystalline organic layer contact one another at an interface; annealing the amorphous organic layer and the crystalline organic layer for a time sufficient to induce at least partial crystallinity in the amorphous organic layer; and depositing a second electrode over the amorphous organic layer and the crystalline organic layer. In the methods and devices herein, the amorphous organic layer may comprise at least one material that undergoes inverse-quasi epitaxial (IQE) alignment to a material of the crystalline organic layer as a result of the annealing.

Abstract: An integrated fan out package on package architecture is utilized along with a reference via in order to provide a reference voltage that extends through the InFO-POP architecture. If desired, the reference via may be exposed and then connected to a shield coating that can be used to shield the InFO-POP architecture. The reference via may be exposed by exposing either a top surface or a sidewall of the reference via using one or more singulation processes.

Abstract: Integrated circuits with improved laterally diffused metal oxide semiconductor (LDMOS) structures, and methods of fabricating the same, are provided. An exemplary LDMOS integrated circuit includes an n-type reduced surface field, a p-type body well disposed on a lateral side of the n-type reduced surface field region, a shallow trench isolation structure disposed within the n-type reduced surface field region, and a gate structure disposed partially over the p-type body well, partially over the n-type reduced surface field region, partially over the shallow trench isolation structure, and partially within the shallow trench isolation structure.

Abstract: A mask assembly includes: a mask frame; and a mask sheet disposed on the mask frame, wherein the mask sheet is stretched by applying tensile force and affixed onto the mask frame, wherein the mask sheet includes a pattern including a plurality of openings, and wherein a thickness of the pattern is different from thicknesses of other portions of the mask sheet.

Abstract: The present invention provides a structure and a method of reinforcing a conductor soldering point of a semiconductor device. The structure includes an inner frame lead, a soldering area arranged on the surface of the inner frame lead, a conductor soldered in the soldering area, and a locking card including a pressing part, a locking part overhangs outwards from the pressing part pressed on the conductor. The locking part penetrates through the inner frame lead and is clamped on the side of the inner frame lead deviating from the conductor. According to the present invention, the conductor soldered on the inner frame lead is firmly clamped on the inner frame lead through the locking card to effectively avoid the stripping condition of the conductor and the inner frame lead, reinforce the electrical connection of the conductor and the inner frame lead, and improve the reliability of the semiconductor device.

Abstract: Provided is a semiconductor device. In some examples, the semiconductor device includes an fin active region protruding from a substrate, gate patterns disposed on the fin active region, a source/drain region disposed on the fin active region between the gate patterns, and contact patterns disposed on the source/drain region. The source/drain region may have a protruding middle section, which may form a wave-shaped upper surface of the source/drain region.

Abstract: A method of forming a FinFET with a rounded source/drain profile comprises forming a fin in a substrate, etching a source/drain recess in the fin, forming a plurality of source/drain layers in the source/drain recess; and etching at least one of the plurality of source/drain layers. The source/drain layers may be a silicon germanium compound. Etching at the source/drain layers may comprises partially etching each of the plurality of source/drain layers prior to forming subsequent layers of the plurality of source/drain layers. The source/drain layers may be formed with a thickness at a top corner of about 15 nm, and the source/drain layers may each be etched back by about 3 nm prior to forming subsequent layers of the plurality of source/drain layers. Forming the plurality of source/drain layers optionally comprises forming at least five source/drain layers.

Abstract: An embodiment is a structure including a first fin over a substrate, a second fin over the substrate, the second fin being adjacent the first fin, an isolation region surrounding the first fin and the second fin, a gate structure along sidewalls and over upper surfaces of the first fin and the second fin, the gate structure defining channel regions in the first fin and the second fin, a source/drain region on the first fin and the second fin adjacent the gate structure, and an air gap separating the source/drain region from a top surface of the substrate.