Abstract: Provided are an atomic layer junction oxide, a method of preparing the atomic layer junction oxide, and a photoelectric conversion device including the atomic layer junction oxide. The atomic layer junction oxide can include an n-type doped atomic layer oxide; an intrinsic atomic layer oxide; a p-type doped atomic layer oxide; and an intrinsic atomic layer oxide.

Abstract: Disclosed herein is a white organic light emitting device including various emission layers with improved luminous efficiency, an increased color viewing angle, and low power consumption. The white organic light emitting device includes at least two charge generation layers and at least three stacks between a first electrode and a second electrode. The first stack includes an emission layer having a wavelength range of about 440 to about 470 nm, the second stack includes an emission layer having a wavelength range of about 530 to about 570 nm, and the third stack includes an emission layer having a wavelength range of about 590 to about 620 nm and an emission layer having a wavelength range of about 440 to about 470 nm.

Abstract: Lamination transfer films and methods for transferring a structured layer to a receptor substrate. The transfer films include a carrier substrate having a releasable surface, a sacrificial template layer applied to the releasable surface of the carrier substrate and having a non-planar structured surface, and a thermally stable backfill layer applied to the non-planar structured surface of the sacrificial template layer. The sacrificial template layer is capable of being removed from the backfill layer, such as via pyrolysis, while leaving the structured surface of the backfill layer substantially intact.

Abstract: An integrated inductor includes a patterned ground shield, an inner rail, and an inductor. The patterned ground shield is disposed in a first direction. The inner rail is coupled to the patterned ground shield. The inner rail is disposed inside the integrated inductor and in a second direction. The first direction is perpendicular to the second direction. The inductor is disposed above the patterned ground shield.

Abstract: Aspects of the present invention relate to approaches for forming a narrow source-drain contact in a semiconductor device. A contact trench can be etched to a source-drain region of the semiconductor device. A titanium liner can be deposited in this contact trench such that it covers substantially an entirety of the bottom and walls of the contact trench. An x-metal layer can be deposited over the titanium liner on the bottom of the contact trench. A titanium nitride liner can then be formed on the walls of the contact trench. The x-metal layer prevents the nitriding of the titanium liner on the bottom of the contact trench during the formation of the nitride liner.

Abstract: A method comprises forming an etch stop layer, a first titanium layer, a magnetic core, a second titanium layer, and patterning the first and second titanium layers. The etch stop layer is formed above a substrate. The first titanium layer is formed on the etch stop layer. The magnetic core is formed on the first titanium layer. The second titanium layer has a first portion encapsulating the magnetic core with the first titanium layer, and a second portion interfacing with the first titanium layer beyond the magnetic core. The patterning of the first and second titanium layers includes forming a mask over a magnetic core region and etching the first and second titanium layers exposed by the mask using a titanium etchant and a titanium oxide etchant.

Abstract: A method of image sensor fabrication includes providing a semiconductor material, an insulation layer, and a logic layer, where the semiconductor material includes a plurality of photodiodes. A through-semiconductor-via is formed which extends from the semiconductor material, through the insulation layer, and into the logic layer. The through-semiconductor-via is capped with a capping layer. A metal pad is disposed in a first trench in the semiconductor material. Insulating material is deposited on the capping layer, and in the first trench in the semiconductor material. A resist is deposited in a second trench in the insulating material, and the second trench in the insulating material is aligned with the metal pad. The insulating material is removed to expose the capping layer, and a portion of the capping layer disposed proximate to the plurality of photodiodes is also removed. A metal grid is formed proximate to the plurality of photodiodes.

Abstract: Disclosed herein is an electroluminescence element that is excellent in color rendering properties and has a long service life as a white light-emitting element, that is, high durability. The electroluminescence element (100) includes: a substrate (1); a first electrode (2); a functional layer (20) including at least one light-emitting layer (5); and a second electrode (8), wherein the at least one light-emitting layer (5) contains a quantum dot material (11), and wherein when a particle size at a cumulative frequency of 10% and a particle size at a cumulative frequency of 90% in a volume-based cumulative particle size distribution of the quantum dot material (11) are defined as d10 (nm) and d90 (nm), respectively, the quantum dot material (11) satisfies d90?d10?3 nm.

Abstract: Provided is a self-supporting polycrystalline GaN substrate composed of GaN-based single crystal grains having a specific crystal orientation in a direction approximately normal to the substrate. The crystal orientations of individual GaN-based single crystal grains as determined from inverse pole figure mapping by EBSD analysis on the substrate surface are distributed with tilt angles from the specific crystal orientation, the average tilt angle being 1 to 10°. There is also provided a light emitting device including the self-supporting substrate and a light emitting functional layer, which has at least one layer composed of semiconductor single crystal grains, the at least one layer having a single crystal structure in the direction approximately normal to the substrate. The present invention makes it possible to provide a self-supporting polycrystalline GaN substrate having a reduced defect density at the substrate surface, and to provide a light emitting device having a high luminous efficiency.

Abstract: Method and structural embodiments are described which provide an integrated structure using polysilicon material having different optical properties in different regions of the structure.

Abstract: Magnetic random access memory (MRAM) devices, and methods of manufacturing the same, include at least one first magnetic material pattern on a substrate, at least one second magnetic material pattern on the at least one first magnetic material pattern, and at least one tunnel barrier layer pattern between the at least one first magnetic material pattern and the at least one second magnetic material pattern. A width of a top surface of the at least one first magnetic material pattern may be less than a width of a bottom surface of the at least one second magnetic material pattern.

Abstract: An array substrate is provided. The array substrate includes: a substrate; a LTPS TFT disposed above the substrate; a planarization layer covering the LTPS TFT; a via hole formed in the planarization layer, wherein the via hole reveals a drain electrode of the LTPS TFT; multiple common electrodes and receiving electrodes disposed separately on the planarization layer, wherein the multiple common electrode function as a driving electrode in a touch stage, and the multiple common electrodes which are disposed separately are connected with each other; a passivation layer which covers the multiple common electrodes and the multiple receiving electrodes and the planarization layer; and a pixel electrode disposed on the passivation layer, wherein, the pixel electrode is contacted with the drain electrode through the via hole. A manufacturing method for the array substrate is also provided. The present invention can reduce one manufacturing process and decrease production cost.

Abstract: An interconnection structure fabrication method is provided. The method includes providing a substrate; forming a conductive film with a first thickness and having a first lattice structure and a first grain size, wherein the first thickness is greater than the first grain size; and performing an annealing process to change the first lattice structure of the conductive film to a second lattice structure and to change the first grain size to a second grain size. The second grain size is greater than the first grain size, and the first thickness is greater than or equal to the second grain size. The method also includes etching portion of the conductive film to form at least one conductive layer; etching portion of the conductive layer to form at least one trench having a depth smaller than the first thickness in the conductive layer to form an electrical interconnection wire and conductive vias; and forming a dielectric layer covering the substrate, sidewalls of the conductive layer, and the trench.

Abstract: A method for uniform fin reveal depth for semiconductor devices includes dry etching a dielectric material to reveal semiconductor fins by a quasi-atomic layer etching (quasi-ALE) process to achieve depth uniformity across different fin pitches. A lateral bias induced by the quasi-ALE process is compensated for by isotropically etching the dielectric material.

Abstract: An organic light-emitting display apparatus is provided. The apparatus includes an organic light-emitting diode emitting visible light, a driving thin film transistor driving the organic light-emitting diode, and a compensation thin film transistor. The compensation thin film transistor includes a compensation gate electrode, a compensation semiconductor layer, a compensation source electrode, and a compensation drain electrode. The compensation gate electrode includes a first gate electrode, and a second gate electrode electrically connected to the first gate electrode. The compensation drain electrode is electrically connected to the driving gate electrode of the driving thin film transistor.

Abstract: III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.

Abstract: There are provided a method of manufacturing a thin film transistor and a display including a thin film transistor. The method of manufacturing a thin film transistor includes forming a barrier layer cm a substrate, forming a semiconductor layer on the barrier layer, forming a gate insulating layer on the semiconductor layer, forming a gate electrode on the gate insulating layer, forming an offset region on an external surface of the gate electrode through a plasma heat treatment process or an annealing process, etching, an offset region of the gate electrode, etching a gate insulating layer except for a portion of the gate insulating layer, positioned below the gate electrode, forming an interlayer insulating layer on the gate electrode, and etching, the interlayer insulating layer to form a source electrode and a drain electrode.

Abstract: According to an embodiment, a semiconductor memory device comprises: a first semiconductor layer extending in a first direction; a first wiring line extending in a second direction intersecting the first direction; a variable resistance layer provided between these first wiring line and first semiconductor layer; and a first gate electrode extending in the first direction and facing the first semiconductor layer via a first insulating layer. In addition, this semiconductor memory device comprises a second gate electrode provided in the first direction with respect to the first wiring line, extending in the second direction in parallel to the first wiring line, and facing the first semiconductor layer. This second gate electrode faces the first semiconductor layer via a second insulating layer. Moreover, this second gate electrode faces the first gate electrode via the second insulating layer, the first semiconductor layer, and the first insulating layer.

Abstract: A method for making a thin film transistor includes a step of forming a semiconducting layer, a source electrode, a drain electrode, a gate electrode, and an insulating layer on an insulating substrate. A process of forming the semiconducting layer comprises a step of sputtering an oxide semiconductor film on a substrate by using a sputtering target comprising In2CexZnO4+2x, wherein x=0.5˜2.

Abstract: Provided is a resin sheet, wherein in a stress measurement in which a dynamic shear strain is applied in a direction parallel to a surface, the difference between a loss tangent as measured when a strain amplitude is 10% of the sheet thickness and a loss tangent as measured when the amplitude is 0.1% is equal to or greater than 1 at a temperature of 80° C. and a frequency of 0.5 Hz. The resin sheet of the present invention can provide a semiconductor device with excellent connection reliability, wherein air bubbles and cracks are less likely to occur in the resin sheet. In the resin composition of the present invention, aggregates are less likely to occur during storage. The resin sheet obtained by forming the resin composition into a sheet has good flatness. The hardened material thereof can provide a circuit board or a semiconductor device with high connection reliability.