Patents Examined by William Bunch
  • Patent number: 4908330
    Abstract: A process for the formation of a functional deposited film as a thin semiconductor film constituted with the group IV element or a thin semiconductor film constituted with group IV element alloy, by introducing, into a film forming space, a compound as the film-forming raw material and, if required, a compound containing an element capable of controlling valence electrons for the deposited film as the constituent element each in a gaseous state, or in a state where at least one of the compounds is activated, while forming hydrogen atoms in an excited state causing chemical reaction with at least one of the compounds in the gaseous state or in the activated state in an activation space different from the film forming space and introducing them into the film forming space, thereby forming a deposited film on a substrate, wherein the hydrogen atoms in the excited state are formed from a hydrogen gas or a gas mixture composed of a hydrogen gas and a rare gas by means of a microwave plasma generated in a plasma ge
    Type: Grant
    Filed: January 27, 1989
    Date of Patent: March 13, 1990
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takayoshi Arai, Masahiro Kanai, Soichiro Kawakami, Tsutomu Murakami
  • Patent number: 4908325
    Abstract: The thickness of a selected layer in an epitaxial heterojunction transistor is initially set to the exact desired value upon its formation, preferably by molecular beam epitaxy, and its thickness is left virtually unaltered during the rest of the fabrication process. Means are provided to prevent alteration of this thickness during subsequent exposure of the selected layer.
    Type: Grant
    Filed: November 9, 1988
    Date of Patent: March 13, 1990
    Assignee: TRW Inc.
    Inventor: John J. Berenz
  • Patent number: 4906583
    Abstract: A semiconductor photodetector, such as a PIN photodiode and an avalanche photodiode, comprising an InP substrate, a first InP layer, a GaInAs or GaInAsP light absorbing layer, and a second InP layer. All of the layers are successively grown by a vapor phase epitaxial process wherein the lattice constant of the GaInAs (GaInAsP) layer is larger than that of the InP layer at room temperature. The photodetector has a low dark current.
    Type: Grant
    Filed: August 22, 1988
    Date of Patent: March 6, 1990
    Assignee: Fujitsu Limited
    Inventors: Shuzo Kagawa, Junji Komeno
  • Patent number: 4904617
    Abstract: A method for separating laser diodes. The diodes are monolithically produced from a semiconductor substrate wafer which through an epitaxy process has been provided with a layer sequence suitable for laser operation. First, the semiconductor substrate wafer is covered with a first mask which defines the interspaces between the mirrors of adjacent laser diodes. Then the mirror surfaces are etched out of the semiconductor substrate wafer. Thereafter, the wafer is covered with a second mask for defining separation trench areas between the mirror surfaces of adjacent laser diodes and for protecting the remaining wafer parts. Then, separation are etched into the trench area. Finally, the laser diodes are separated by breaking the wafer along the trenches. In a preferred embodiment, the wafer thickness is at most twice the distance between the mirror surfaces of adjacent laser diodes and the trench depth is at least one fourth of the wafer thickness.
    Type: Grant
    Filed: August 25, 1988
    Date of Patent: February 27, 1990
    Assignee: Siemens Aktiengesellschaft
    Inventor: Markus Muschke
  • Patent number: 4904616
    Abstract: The present invention addresses the use of at least partially fluorinated organometallic compounds in reactive deposition applications. More specifically, the present invention addresses the use of the fluoroorganometallic compounds M(CF.sub.3).sub.3, M(CF.sub.2 CF.sub.3).sub.3, or any M(C.sub.n F.sub.(2n+1)).sub.3-y H.sub.y compound where (y.ltoreq.2), M(CH.sub.2 CF.sub.3).sub.3 or any fluoroalkyl organometallics of the general formula M(C.sub.n H.sub.[(2n+1)-x] F.sub.x).sub.3-y H.sub.y, where y.ltoreq.2; x has a value 1.ltoreq.x.ltoreq.2n+1; and M=As, P, or Sb, in processes requiring deposition of the corresponding element. These uses include a number of different processes; the organometallic vapor phase epitaxy of compound semiconductor materials such as GaAs, InP, AlGaAs, InSb, etc.; doping of SiO.sub.
    Type: Grant
    Filed: July 25, 1988
    Date of Patent: February 27, 1990
    Assignee: Air Products and Chemicals, Inc.
    Inventors: David A. Bohling, Gregory T. Muhr, David A. Roberts
  • Patent number: 4902642
    Abstract: The present invention provides products and methods of forming an epitaxial silicon layer on an implanted buried insulator silicon on insulator structure (10). A silicon film (16) is pre-treated to remove residual oxide and surface damage layers, but in such a way as to not damage the silicon film (16) or insulating layer (14) below the silicon film (16). A layer of amorphous silicon (18) is formed on the silicon film (16) in processes to avoid formation of polycrystalline silicon, and also to avoid damage to the silicon film (16). The layer of amorphous silicon (18) is annealed to form an epitaxial layer of single crystalline silicon (20).
    Type: Grant
    Filed: August 24, 1988
    Date of Patent: February 20, 1990
    Assignee: Texas Instruments, Incorporated
    Inventors: Bor-Yen Mao, Richard L. Yeakley
  • Patent number: 4902356
    Abstract: An epitaxial layer having a double-hetero structure is forming using an MOCVD process or an MBE process, and an epitaxial substrate is formed using an LPE process, thereby forming a substrate which exploits the distinguishing features of both processes. Since the MOCVD process or MBE process exhibits mixed-crystal ratio and film thickness controllability, excellent reproducibility and uniformity are obtained when forming the double-hetero structure on a compound semiconductor substrate. Since the growth process takes place under thermal non-equilibrium, the amount of impurity doping is raised to more than 10.sup.19 cm.sup.3. This is advantageous in terms of forming an electrode contact layer. With the LPE process, the material dissolved in the melt is grown epitaxially on the substrate by slow cooling, and the rate of growth is high. This process is suitable for forming the substrate after removal of the compound semiconductor substrate.
    Type: Grant
    Filed: January 19, 1989
    Date of Patent: February 20, 1990
    Assignees: Mitsubishi Monsanto Chemical Company, Mitsubishi Kasei Corporation
    Inventors: Masahiro Noguchi, Hideki Gotoh, Kenji Shimoyama
  • Patent number: 4902643
    Abstract: A method of selective epitaxial growth for compound semiconductor includes the steps of forming a layer of group IV element semiconductor, such as Ge, with a predetermined pattern on a compound semiconductor substrate and forming a compound semiconductor layer selectively on the compound semiconductor substrate by alternately supplying a gas of compound containing a group III or II element, such as trimethylgallium, triethylgallium and triisobutylaluminum, and a gas of compound containing a group V or VI element, such as AsH.sub.3, onto both surface of the layer of group IV element semiconductor and the compound semiconductor substrate. Another semiconductor layer of group IV element semiconductor or compound semiconductor may be formed on the layer of group IV element semiconductor by organometallic vapor phase epitaxy or MBE.
    Type: Grant
    Filed: February 9, 1989
    Date of Patent: February 20, 1990
    Assignee: NEC Corporation
    Inventor: Hidenori Shimawaki
  • Patent number: 4902641
    Abstract: A process for making an inverted silicon-on-insulator semiconductor device having a pedestal structure. After the processing of polysilicon layers, dielectric layers, an epitaxial region and a nitride layer, a second substrate is bonded to the nitride layer and the first substrate is removed. This allows for an epitaxial region which is isolated from the substrate.
    Type: Grant
    Filed: July 31, 1987
    Date of Patent: February 20, 1990
    Assignee: Motorola, Inc.
    Inventor: Daniel N. Koury, Jr.
  • Patent number: 4900694
    Abstract: A process for the preparation of a multi-layers stacked junction typed thin film transister of which electric amplification factor (.beta.) at the time of the base electrode or the emitter electrode being grounded is about 10 and which has an excellent amplifying operation.
    Type: Grant
    Filed: March 21, 1988
    Date of Patent: February 13, 1990
    Assignee: Canon Kabushiki Kaisha
    Inventor: Katsumi Nakagawa
  • Patent number: 4900696
    Abstract: A method for patterning a photo resist film including the steps of coating a photo resist onto a semiconductor substrate exposing the photo resist coated and thereafter developing it, to thereby form a pattern on the photo resist film, wherein after exposure the semiconductor substrate on which the photo resist is coated is left in an atmosphere of a higher relative humidity than that at which the patterning exposure has been conducted for a time period until development.
    Type: Grant
    Filed: December 14, 1988
    Date of Patent: February 13, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasushi Ito, Kazuhiko Urayama
  • Patent number: 4900372
    Abstract: A method for producing wafers having deposited layers of III-V materials on Si or Ge/Si substrates is disclosed. The method involves the use of multiple in situ and ex situ annealing steps and the formation of a thermal strain layer to produce wafers having a decreased incidence of defects and a balanced thermal strain. The wafers produced thereby are also disclosed.
    Type: Grant
    Filed: March 2, 1989
    Date of Patent: February 13, 1990
    Assignee: Kopin Corporation
    Inventors: Jhang W. Lee, Richard E. McCullough
  • Patent number: 4898834
    Abstract: An improved system and method for annealing indium antimonide ion implanted junctions employing an open-tube benign annealing environment. A furnace having a hollow chamber therein is maintained continuously at a predetermined annealing temperature and wafers of indium antimonide to be annealed are inserted into the chamber through a resealable airlock at one end of the chamber. A source of molten indium saturated with antimony is provided within the chamber to maintain desired partial pressures of indium and antimony within the chamber. Hydrogen gas is continuously flushed through the chamber to purge contaminants and maintain the chamber at a desired slight overpressure over atmospheric. At the conclusion of annealing, the indium antimonide wafer is removed from the chamber into the airlock which is flushed with hydrogen gas. The wafer is allowed to cool to room temperature and removed from the airlock for subsequent processing steps.
    Type: Grant
    Filed: June 27, 1988
    Date of Patent: February 6, 1990
    Assignee: Amber Engineering, Inc.
    Inventors: Arthur H. Lockwood, Adela Gonzales
  • Patent number: 4897362
    Abstract: A method of forming a high-quality complementary transistor device using bonded wafer technology. The invention includes bonding a handle wafer to a first epitaxial layer and then providing dopants to form the respective N and P buried layers in said first epitaxial layer. A second epitaxial layer is then deposited over the buried layers to provide the device forming regions for the respective transistor devices.
    Type: Grant
    Filed: September 2, 1987
    Date of Patent: January 30, 1990
    Assignee: Harris Corporation
    Inventors: Jose A. Delgado, George Bajor
  • Patent number: 4897360
    Abstract: Polycrystalline silicon is deposited in a film onto the surface of a substrate which has been carefully prepared to eliminate any defects or contaminants which could nucleate crystal growth on the substrate. The deposition is carried out by low pressure decomposition of silane at substantially 580.degree. C. to cause a film of fine grained crystals of polysilicon to be formed having grain sizes averaging less than about 300 Angstroms after annealing. Such a film is very uniform and smooth, having a surface roughness less than about 100 Angstroms RMS. Annealing of the film and substrate at a low temperature results in a compressive strain in the field that decreases over the annealing time, annealing at high temperatures (e.g., over 1050.degree. C.) yields substantially zero strain in the film, and annealing at intermediate temperatures (e.g., 650.degree. C. to 950.degree. C.) yields tensile strain at varying strain levels depending on the annealing temperature and time.
    Type: Grant
    Filed: December 9, 1987
    Date of Patent: January 30, 1990
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Henry Guckel, David W. Burns
  • Patent number: 4897361
    Abstract: When high-vacuum methods are used in the manufacture of miniaturized devices such as, e.g., semiconductor integrated-circuit devices, device layers on a substrate are preferably patterned without breaking of the vacuum. Preferred patterning involves deposition of a semiconductor mask layer, generation of the pattern in the mask layer by ion deflected-beam writing, and transfer of the pattern by dry etching. When the mask layer is an epitaxial layer, further epitaxial layer deposition after patterning may proceed without removal of remaining mask layer material.
    Type: Grant
    Filed: December 14, 1987
    Date of Patent: January 30, 1990
    Assignee: American Telephone & Telegraph Company, AT&T Bell Laboratories
    Inventors: Lloyd R. Harriott, Morton B. Panish, Henryk Temkin
  • Patent number: 4897367
    Abstract: A GaAs layer having a high crystallinity can be grown over an Si substrate without warping, by process for growing a GaAs layer on an Si substrate, said process comprising: forming a first GaAs layer in the amorphous state on the Si substrate at a first temperature, the first GaAs layer being formed with a thickness allowing formation of a single crystalline layer having a thickness of one to three monomolecular layers; heating the first GaAs layer to change the amorphous state of the first GaAs layer to a single crystalline state; forming an Si layer on the first GaAs layer at a second temperature higher than the first temperature, the Si layer being formed with a thickness having one to six monoatomic layers; forming a second GaAs layer in the amorphous state on the Si layer at the first temperature, the second GaAs layer being formed with a thickness substantially the same as the thickness of the first GaAs layer; heating the second GaAs layer the change the amorphous state of the second GaAs layer to a si
    Type: Grant
    Filed: March 17, 1989
    Date of Patent: January 30, 1990
    Assignee: Fujitsu Limited
    Inventor: Kazuto Ogasawara
  • Patent number: 4894349
    Abstract: A process for forming a vapor-phase epitaxial growth layer on a silicon wafer having a buried layer of a high As or B concentration. This vapor-phase epitaxial growth process is performed in two steps of (i) performing a vapor-phase epitaxial growth at a relatively low temperature by using a reaction gas containing at least one kind selected from a group consisting of SiH.sub.x F.sub.4-x (x=0 to 3) and Si.sub.2 H.sub.x F.sub.6-x (x=0-5) and at least one kind selected from a group consisting of SiH.sub.4 and Si.sub.2 H.sub.6, and (ii) performing a vapor-phase epitaxial growth under a condition which allows a higher growth rate that in the step (i) by using a reaction gas containing SiH.sub.4 or Si.sub.2 H.sub.6 which may or may not be accompanied with silane fluoride.
    Type: Grant
    Filed: December 15, 1988
    Date of Patent: January 16, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiko Saito, Yoshiaki Matsushita
  • Patent number: 4892841
    Abstract: A semiconductor memory device is formed of a polycrystalline silicon electrode terminal layer, which is formed on a MOS transistor except over the gate region and is connected to the drain region of the MOS transistor, and metal wire layer, which is formed on the MOS transistor except over the gate region and is connected to the electrode terminal layer to transmit output signals. Data is written into the semiconductor memory device by ion implantation of the gate of the MOS transistor after the metal wire layer is formed.
    Type: Grant
    Filed: October 11, 1988
    Date of Patent: January 9, 1990
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taira Iwase, Shoji Ariizumi, Fujio Masuoka
  • Patent number: 4891330
    Abstract: A method of fabricating doped microcrystalline semiconductor alloy material which includes a band gap widening element through a glow discharge deposition process by subjecting a precursor mixture which includes a diluent gas to an a.c. glow discharge in the absence of a magnetic field of sufficient strength to induce electron cyclotron resonance.
    Type: Grant
    Filed: March 28, 1988
    Date of Patent: January 2, 1990
    Assignee: Energy Conversion Devices, Inc.
    Inventors: Subhendu Guha, Stanford R. Ovshinsky