Patents Examined by William Bunch
  • Patent number: 4933301
    Abstract: A method of making semiconductor laser arrays having an impurity disordered pattern of waveguides at least some of which are directly joined at branching junctions. The region near the branching junctions provides a phase boundary condition in which lightwaves propagating in adjacent waveguides are in phase. Using one impurity dose and one disordering depth in a first portion of the pattern and another in a second portion of the pattern provides a combination of strong and weak waveguiding with strong waveguides that eliminate evanescent coupling from occurring at least in the branching junction regions, and with weak guides near one or both end facets permitting evanescent coupling. The evanescent coupling between adjacent weak waveguides preserves the in phase relationship that was established in the Y-junction regions, resulting in a diffraction limited single lobe far field output.
    Type: Grant
    Filed: January 27, 1989
    Date of Patent: June 12, 1990
    Assignee: Spectra Diode Laboratories, Inc.
    Inventors: Donald R. Scifres, David Welch, Peter Cross, William Streifer
  • Patent number: 4933299
    Abstract: MOVPE growth and photoetching are integrated into a unified sequence which is carried out without removing a workpiece from a MOVPE reactor. Growth may be carried out before, after or before and after the etching.To prevent pattern broadening by diffussion of the active species the substrate is preferably protected by a fugitive coating which is removed by the illumination. Native oxide coatings are particularly suitable for InGaAsP substrates. These are conveniently applied for exposing to substrate to 20.degree./o O.sub.2 +80.degree./oN.sub.2 for about 3 minutes at 450.degree. C.
    Type: Grant
    Filed: March 13, 1989
    Date of Patent: June 12, 1990
    Assignee: British Telecommunications public limited company
    Inventor: Kenneth Durose
  • Patent number: 4929571
    Abstract: A semiconductor laser includes a semiconductor substrate on which a longitudinal groove is provided in the resonator direction, a first semiconductor layer disposed on a region of the semiconductor substrate where the groove is not provided and forming a rectifying junction therewith, a first cladding layer provided on the semiconductor substrate in the groove, an active layer provided on the first cladding layer in the groove, and a second cladding layer provided directly on the active layer and opposite the first semiconductor layer with an interposed insulating layer, such as a gap void of solid material or a gap and current blocking material having only negligible parasitic capacitance.
    Type: Grant
    Filed: March 10, 1989
    Date of Patent: May 29, 1990
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Etsuji Omura, Hirofumi Namizaki
  • Patent number: 4927781
    Abstract: A method for forming a semiconductor waveguide includes forming a layer of expitaxial silicon over a substrate. The impurity concentration of the layer is higher than that of the substrate. A second layer of epitaxial silicon is disposed over the upper surface of the layer with a higher resistivity than that of the substrate. A masking layer is then disposed over the substrate and then patterned, and then the layer selectively etched down to the upper surface of the layer. The layer is then porified to form an insulating layer from the layer. The porous film is then converted by oxidation to a silicon dioxide layer. The sidewalls of the resulting ridge are then oxidized to form sidewall layers and then the masking layer removed from the upper layer. The upper surface of ridge is oxidized to form an upper insulating layer to extend the sidewall layer over the entire upper surface and sidewalls of the ridge. A layer of insulating material is then disposed over the substrate.
    Type: Grant
    Filed: March 20, 1989
    Date of Patent: May 22, 1990
    Inventor: Robert O. Miller
  • Patent number: 4925810
    Abstract: A compound semiconductor device comprises a substrate formed from a single crystal of silicon, a layer of an insulator formed on a portion of a surface of the substrate, at least one layer of a high resistance compound semiconductor formed on the insulator layer, and at least one layer of a single crystal of a compound semiconductor formed on a different portion of the substrate surface from the insulator layer. The device can be manufactured by forming an insulator layer on one portion of a surface of a single crystal silicon substrate, and growing a compound semiconductor by epitaxy on the insulator layer and on the different portion from the insulator layer. One of useful applications is a hybrid semiconductor device having a compound semiconductor formed from e.g. GaAs on a silicon substrate.
    Type: Grant
    Filed: August 24, 1989
    Date of Patent: May 15, 1990
    Assignee: Kabushiki Kaisha Toyota Chuo Kenkyusho
    Inventors: Hiroyuki Kano, Takatoshi Kato, Masafumi Hashimoto
  • Patent number: 4925811
    Abstract: A double heterostructure stack comprising confinement layers (CC) enclosing active layers (CA) is formed on a substrate (S), e.g. a N+ type gallium arsenide substrate. Selective etching is performed so as to lay bare the confinement layers at different depths, e.g. CC4, CC3, CC2. The confinement layers initially receive contact layers (CP) made of P-type gallium arsenide. Regions R1, R2, and R3 are formed through the contact layers to constitute junctions with the uppermost active layers (respectively CA1, CA2, CA3). Valleys (V10, V21, V32) are formed to isolate the above-defined elementary stacks. After a metal contact layer has been formed, and after the end surfaces have been optically prepared, a multi-wavelength laser device is obtained.
    Type: Grant
    Filed: June 30, 1988
    Date of Patent: May 15, 1990
    Assignee: L'Etat Francais represente par le Ministre Des Postes Et Telecommunications - Centre National d'Etudes des Telecommunications
    Inventors: Louis Menigaux, Louis Dugrand
  • Patent number: 4920069
    Abstract: Submicron structure fabrication is accomplished by providing vapor chemical erosion of a compound crystal by suppressing the more volatile elements so that the less volatile element is provided with an anti-agglomeration and erosion rate limiting capability which can be followed by subsequent regrowth in the same environment. The erosion is sensitive to crystallographic orientation.
    Type: Grant
    Filed: April 15, 1988
    Date of Patent: April 24, 1990
    Assignee: International Business Machines Corporation
    Inventors: Eric R. Fossum, Peter D. Kirchner, George D. Pettit, Alan C. Warren, Jerry M. Woodall
  • Patent number: 4920068
    Abstract: A process to produce one or more Group II-VI epitazial layers over a crystalline substrate by directing flows of one or more Group II components and a Group VI metalorganic vapor to a heated substrate whereby the vapors thereby react to form the epitaxial layer(s), is improved in terms of lower reaction temperatures and higher product quality if, as the Group VI metalorganic vapor source, there is used a tellurium compound of the formula: ##STR1## wherein R.sup.1 and R.sup.2 are, independently, hydrogen or C.sub.1 -C.sub.4 alkyl, preferably, hydrogen.
    Type: Grant
    Filed: April 2, 1986
    Date of Patent: April 24, 1990
    Assignee: American Cyanamid Company
    Inventors: Donald Valentine, Jr., Duncan W. Brown
  • Patent number: 4918028
    Abstract: A process for forming deposited film, which comprises:(a) the step of preparing a substrate having crystal nuclei or regions where crystal nuclei are selectively formed scatteringly on the surface for forming deposited film in a film forming space for formation of deposited film;(b) the step of forming deposited film on the above substrate by introducing an activated species (A) formed by decomposition of a compound (SX) containing silicon and a halogen and an activated species (B) formed from a chemical substance for film formation (B) which is chemically mutually reactive on said activated species (A) separately from each other into said film-forming space to effect chemical reaction therebetween;(c) the step of introducing a gaseous substance (E) having etching action on the deposited film to be formed or a gaseous substance (E.sub.
    Type: Grant
    Filed: October 21, 1988
    Date of Patent: April 17, 1990
    Assignee: Canon Kabushiki Kaisha
    Inventor: Shigeru Shirai
  • Patent number: 4916089
    Abstract: In order, in the epitaxial production of semiconductor products and of articles provided with a layer, to be able to make the junction between the layers applied to the substrates atomically sharp, it is important to be able to change the gas mixture, to be introduced into a pulsed reactor or MBE reactor, rapidly, accurately and without losses in respect of quantity and of composition. To this purpose, each of the gases to be introduced into the reactor is conveyed to a separate gas pipette and thereafter the content of the gas pipette is cyclically passed, by means of a pressure differential, into the pulse reactor, with the composition of the mixture being changed per one or more cycles.
    Type: Grant
    Filed: September 2, 1988
    Date of Patent: April 10, 1990
    Assignee: Stichting Katholieke Universiteit
    Inventors: Jaap Van Suchtelen, Lodevicus J. Giling, Josephus E. M. Hogenkamp
  • Patent number: 4916088
    Abstract: A low dislocation density semiconductor device includes a first semiconductor layer of a III-V or II-VI semiconductor compound and alloying atoms on a non-metal substrate. The semiconductor compound usually has a large dislocation density. A predetermined position of the alloying atoms in the compound lattice structure can substantially reduce the compound dislocation density. Energy is applied to the alloying atoms so they are at the predetermined positions. The number of alloying atoms causes the semiconductor compound solubility limit to be exceeded. The layer is formed on a substrate of the III-V or II-VI semiconductor, such as gallium arsenide or another semiconductor, such as silicon or on an insulator such as sapphire. In the latter cases, the layer is formed on an intermediate layer having a lattice constant between that of the substrate and semiconductor compound.
    Type: Grant
    Filed: April 29, 1988
    Date of Patent: April 10, 1990
    Assignee: SRI International
    Inventors: John B. Mooney, Arden Sher
  • Patent number: 4914052
    Abstract: A process for the formation of a functional deposited film containing atoms belonging to the group III and V of the peridoical table as the main constituent atoms by introducing, into a film forming space for forming a deposited film on a substrate disposed therein, a group III compound (1) and a group IV compound (2) as the film-forming raw material and, if required, a compound (3) containing an element capable of controlling valence electrons for the deposited film as the constituent element each in a gaseous state, or in a state where at least one of such compounds is previously activated in an activation space disposed separately from the film forming space, while forming hydrogen atoms in excited state which cause chemical reaction with at least one of the compounds (1), (2) and (3) in the gaseous state or in the activated state in an activation space different from the film forming space and introducing them into the film-forming space, thereby forming the functional deposited film on the substrate, whe
    Type: Grant
    Filed: January 27, 1989
    Date of Patent: April 3, 1990
    Assignee: Canon Kabushiki Kaisha
    Inventor: Masahiro Kanai
  • Patent number: 4914053
    Abstract: Preferred embodiments include growth of GaAs on insulator-masked silicon; the GaAs is single crystal over the silicon but polycrystalline over the insulator. A post=growth anneal extends the single crystal region over the insulator for distances of 2-4 .mu.m.
    Type: Grant
    Filed: September 8, 1987
    Date of Patent: April 3, 1990
    Assignee: Texas Instruments Incorporated
    Inventors: Richard J. Matyi, Hisashi Shichijo
  • Patent number: 4910165
    Abstract: A silicon on insulator fabrication process and structure. The fabrication process includes a reproducible sequence in which an oxide covered substrate is anisotropically etched in the presence of a mask to form trenches which extend into the substrate. Epitaxial silicon is selectively grown in the trench regions in a sucession of first materially doped and thereafter lightly doped layers. The materially doped layer extends above the plane defined by the surface of the substrate. Following a selective removal of the oxide, the materially doped epitaxial layer is exposed at its sidewalls first to an anodization and then to an oxidation ambient. This successive conversion of the materially doped epitaxial layer first to porous silicon and then silicon dioxide dielectric isolates the lightly doped epitaxial layer from the substrate.
    Type: Grant
    Filed: November 4, 1988
    Date of Patent: March 20, 1990
    Assignee: NCR Corporation
    Inventors: Steven S. Lee, Dim-Lee Kwong
  • Patent number: 4910164
    Abstract: A lift-off method for forming regions of a first semiconductor such as GaAs (104) in recesses in a substrate of a second semiconductor such as silicon (102) with the surface of the first semiconductor region (104) coplanar with the surface of the second semiconductor layer (102). Also, interconnected devices in both regions. Preferred embodiment methods include growth by molecular beam epitaxy of a layer of the first semiconductor on a masked and recessed substrate of the second semiconductor followed by photolithographic removal of the grown layer outside of a neighborhood of the recesses and lift-off (by mask etching) of the remainder of the grown layer outside of the recesses.
    Type: Grant
    Filed: July 27, 1988
    Date of Patent: March 20, 1990
    Assignee: Texas Instruments Incorporated
    Inventor: Hisashi Shichijo
  • Patent number: 4910163
    Abstract: Silicon epitaxial layers are grown on oriented silicon substrates using an open-tube Si-I.sub.2 chemical vapor deposition (CVD) reactor in the temperature range of 650.degree.-740.degree. C. Hydrogen and inert gases such as helium and argon are used as carrier gases, and the iodine/carrier gas mixture contacts the silicon source to produce silicon iodide which disproportionates to deposit pure silicon epitaxial layers on the substrate.
    Type: Grant
    Filed: June 9, 1988
    Date of Patent: March 20, 1990
    Assignee: University of Connecticut
    Inventor: Faquir C. Jain
  • Patent number: 4910167
    Abstract: A GaAs containing nucleation layer is deposited upon Si, Ge/Si, or other single crystal substrate from triethyl gallium (TEG). Deposition from TEG allows a lower deposition temperature which provides a low level of substrate contamination and improved surface morphology.
    Type: Grant
    Filed: November 13, 1987
    Date of Patent: March 20, 1990
    Assignee: Kopin Corporation
    Inventors: Jhang W. Lee, Richard E. McCullough, Jack P. Salerno
  • Patent number: 4910166
    Abstract: Bars of integral laser diode devices cleaved from a wafer are placed with their p regions abutting and n regions abutting. A thin BeCu mask having alternate openings and strips of the same width as the end facets is used to mask the n region interfaces so that multiple bars can be partially coated over their exposed p regions with a reflective or partial reflective coating. The partial coating permits identification of the emitting facet from the fully coated back facet during a later device mounting procedure.
    Type: Grant
    Filed: January 17, 1989
    Date of Patent: March 20, 1990
    Assignee: General Electric Company
    Inventor: Anil R. Dholakia
  • Patent number: 4908329
    Abstract: A process for the formation of a functional deposited film containing atoms belonging to the group II and VI of the periodical table as the main constituent atoms by introducing, into a film forming space for forming a deposited film on a substrate disposed therein, a group II compound (1) and a group VI compound (2) as the film-forming raw material and, if required, a compound (3) containing an element capable of controlling valence electrons for the deposited film as the constituent element each in a gaseous state, or in a state where at least one of such compounds is previously activated in an activation space disposed separately from the film forming space, while forming hydrogen atoms in an excited state which cause chemical reaction with at least one of the compounds (1), (2) and (3) in the gaseous state or in the activated state in an activation space different from the film forming space and introducing them into the film-forming space, thereby forming the functional deposited film on the substrate, w
    Type: Grant
    Filed: January 27, 1989
    Date of Patent: March 13, 1990
    Assignee: Canon Kabushiki Kaisha
    Inventors: Masahiro Kanai, Tsutomu Murakami, Takayoshi Arai, Soichiro Kawakami
  • Patent number: 4908074
    Abstract: Disclosed is a process for the production of a semiconductor element by introducing a gas of an organic metal compound of an element of the group III and a gas containing an element of the group V into a reaction chamber in which a substrate of a single crystal of alumina is arranged and epitaxially growing a III.V compound semiconductor by the thermal decomposition vapor deposition of the compound of the elements of the groups III.V, said process comprises, in combination, the steps of (A) heating the substrate at a temperature of 400.degree. to 550.degree. C., introducing the gas of the organic metal compound of the element of the group III and the gas containing the element of the group V into the reaction chamber and forming a film of a compound of the elements of the groups III.V on the surface of the substrate by the vapor deposition, (B) heating the substrate obtained at the step (A) at a temperature higher than 550.degree. C. but lower than 750.degree. C.
    Type: Grant
    Filed: December 6, 1988
    Date of Patent: March 13, 1990
    Assignee: Kyocera Corporation
    Inventors: Takashi Hosoi, Kokichi Ishibitsu