Patents Examined by William D. Coleman
  • Patent number: 9525148
    Abstract: A device including an emissive material comprising quantum dots is disclosed. In one embodiment, the device includes a first electrode and a second electrode, a layer comprising quantum dots disposed between the first electrode and the second electrodes, and a first interfacial layer disposed at the interface between a surface of the layer comprising quantum dots and a first layer in the device. In certain embodiments, a second interfacial layer is optionally further disposed on the surface of the layer comprising quantum dots opposite to the first interfacial layer. In certain embodiments, a device comprises a light-emitting device. Other light emitting devices and methods are disclosed.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: December 20, 2016
    Assignee: QD VISION, INC.
    Inventors: Peter T. Kazlas, Zhaoqun Zhou, Yuhua Niu, Sang-Jin Kim, Benjamin S. Mashford
  • Patent number: 9293201
    Abstract: A memory device includes a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. The formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer.
    Type: Grant
    Filed: February 21, 2014
    Date of Patent: March 22, 2016
    Assignee: 4D-S PTY, LTD
    Inventor: Dongmin Chen
  • Patent number: 9224607
    Abstract: A semiconductor device includes a first device region and second device region of opposite polarity. Each device region includes at least a transistor device and associated epitaxy. A high-k barrier is formed to overlay the first device region epitaxy only. The high-k barrier may include a substantially horizontal portion formed upon a top surface of the first device region epitaxy and a substantially vertical portion formed upon an outer surface of the first device region epitaxy. The substantially vertical portion may partially isolate the first device region from the second device region.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: December 29, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Kangguo Cheng, Ali Khakifirooz, Shom Ponoth, Raghavasimhan Sreenivasan
  • Patent number: 9214352
    Abstract: Embodiments of an ohmic contact structure for a Group III nitride semiconductor device and methods of fabrication thereof are disclosed. In one embodiment, the ohmic contact structure has less than or equal to 5%, more preferably less than or equal to 2%, more preferably less than or equal to 1.5%, and even more preferably less than or equal to 1% degradation for 1000 hours High Temperature Soak (HTS) at 300 degrees Celsius. In another embodiment, the ohmic contact structure additionally or alternatively has less than or equal to 10% degradation, more preferably less than or equal to 7.5% degradation, more preferably less than or equal to 6% degradation, more preferably less than or equal to 5% degradation, and even more preferably less than 3% degradation for 1000 hours High Temperature operating Life (HToL) at 225 degrees Celsius and 50 milliamps (mA) per millimeter (mm).
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: December 15, 2015
    Assignee: Cree, Inc.
    Inventors: Helmut Hagleitner, Daniel Namishia
  • Patent number: 9190579
    Abstract: A method for manufacturing a light emitting device that comprises a light emitting element and a phosphor layer to absorb at least a part of light emitted from the light emitting element to emit a light having a different wavelength from that of the absorbed light comprises a first resin layer forming step of forming a first resin layer with a first resin in which viscosity is adjusted to a first viscosity on a light emitting face of the light emitting element to define a predetermined shape of the phosphor layer; a second resin layer forming step of forming a second resin layer with a second resin containing a phosphor in which viscosity is adjusted to a second viscosity lower than the first viscosity on the first resin layer before curing the first resin layer; and a curing step of curing the first resin layer and the second resin layer.
    Type: Grant
    Filed: October 25, 2013
    Date of Patent: November 17, 2015
    Assignee: NICHIA CORPORATION
    Inventors: Takashi Sato, Hiroshi Miyairi, Kazunori Watanabe
  • Patent number: 9134459
    Abstract: An optical component is disclosed that comprises a first substrate, an optical material comprising quantum confined semiconductor nanoparticles disposed over a predetermined region of a first surface of the first substrate, a layer comprising an adhesive material disposed over the optical material and any portion of the first surface of the first substrate not covered by the optical material, and a second substrate disposed over the layer comprising an adhesive material, wherein the first and second substrates are sealed together. In certain embodiments, the optical component further includes a second optical material comprising quantum confined semiconductor nanoparticles disposed between the layer comprising the adhesive material and the second substrate. Method are also disclosed. Also disclosed are products including the optical component.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: September 15, 2015
    Assignee: QD VISION, INC.
    Inventors: John R. Linton, Emily M. Squires, Rohit Modi, David Gildea
  • Patent number: 9129952
    Abstract: Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.
    Type: Grant
    Filed: September 23, 2013
    Date of Patent: September 8, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Suk Shin, Hyun-Chul Kang, Dong-Hyun Roh, Pan-Kwi Park, Geo-Myung Shin, Nae-In Lee, Chul-Woong Lee, Hoi-Sung Chung, Young-Tak Kim
  • Patent number: 9105523
    Abstract: A reduction in contaminating impurities in a TFT, and a TFT which is reliable, is obtained in a semiconductor device which uses the TFT. By removing contaminating impurities residing in a film interface of the TFT using a solution containing fluorine, a reliable TFT can be obtained.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: August 11, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masaya Kadono, Shunpei Yamazaki, Yukio Yamauchi, Hidehito Kitakado
  • Patent number: 9093435
    Abstract: A method of making a microelectronic package includes forming a dielectric encapsulation layer on an in-process unit having a substrate having a first surface and a second surface remote therefrom. A microelectronic element is mounted to the first surface of the substrate, and a plurality of conductive elements exposed at the first surface, at least some of which are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the bases and define an edge surface extending away between the base and the end surface. The encapsulation layer is formed to at least partially cover the first surface and portions of the wire bonds with unencapsulated portions of the wire bonds being defined by at least one of the end surface or a portion of the edge surface that is uncovered thereby.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: July 28, 2015
    Assignee: Tessera, Inc.
    Inventors: Hiroaki Sato, Teck-Gyu Kang, Belgacem Haba, Philip R. Osborn, Wei-Shun Wang, Ellis Chau, Ilyas Mohammed, Norihito Masuda, Kazuo Sakuma, Kiyoaki Hashimoto, Kurosawa Inetaro, Tomoyuki Kikuchi
  • Patent number: 9070626
    Abstract: Embodiments of an ohmic contact structure for a Group III nitride semiconductor device and methods of fabrication thereof are disclosed. In one embodiment, the ohmic contact structure has less than or equal to 5%, more preferably less than or equal to 2%, more preferably less than or equal to 1.5%, and even more preferably less than or equal to 1% degradation for 1000 hours High Temperature Soak (HTS) at 300 degrees Celsius. In another embodiment, the ohmic contact structure additionally or alternatively has less than or equal to 10% degradation, more preferably less than or equal to 7.5% degradation, more preferably less than or equal to 6% degradation, more preferably less than or equal to 5% degradation, and even more preferably less than 3% degradation for 1000 hours High Temperature operating Life (HToL) at 225 degrees Celsius and 50 milliamps (mA) per millimeter (mm).
    Type: Grant
    Filed: July 14, 2011
    Date of Patent: June 30, 2015
    Assignee: Cree, Inc.
    Inventors: Helmut Hagleitner, Daniel Namishia
  • Patent number: 9059046
    Abstract: A thin film transistor array panel according to an exemplary embodiment of the invention includes: a substrate; a gate line positioned on the substrate and including a gate electrode; a gate insulating layer positioned on the gate line; an oxide semiconductor layer positioned on the substrate; a source electrode and a drain electrode positioned on the oxide semiconductor layer; a first insulating layer positioned on the source electrode and the drain electrode and including a first contact hole; a data line positioned on the first insulating layer and intersecting the gate line; and a pixel electrode over the first insulating layer. The source electrode and the drain electrode each comprise a metal oxide. The data line is electrically connected to the source electrode through the first contact hole.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: June 16, 2015
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Shin Il Choi, Seung-Ha Choi, Bong-Kyun Kim, Sang Gab Kim, Sho Yeon Kim, Hyun Kim, Hong Sick Park, Su Bin Bae
  • Patent number: 9054150
    Abstract: The invention relates to a semiconductor component comprising a semiconductor body, an insulation on the semiconductor body and a cell array arranged at least partly within the semiconductor body. The cell array has at least one p-n junction and at least one contact connection. The insulation is bounded in lateral direction of the semiconductor body by a circumferential diffusion barrier.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: June 9, 2015
    Assignee: Infineon Technologies AG
    Inventors: Markus Zundel, Gabriela Brase, Peter Nelle, Guenther Schindler
  • Patent number: 9054002
    Abstract: A process of forming an isolation region that defines an active region on a semiconductor wafer, a process of forming a photoelectric conversion element in the active region defined by the isolation region, and a process of forming a micro lens over the photoelectric conversion element are provided. Alignment in the process of forming the photoelectric conversion element and alignment in the process of forming the micro lens are performed using an alignment mark formed in the process of forming the isolation region.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: June 9, 2015
    Assignee: Canon Kabushiki Kaisha
    Inventors: Mikio Arakawa, Masataka Ito
  • Patent number: 9054261
    Abstract: The photodiode device has an electrically conductive cathode layer (3) at a photodiode layer (4) composed of a semiconductor material. Doped anode regions (5) are situated at a top side of the photodiode layer facing away from the cathode layer. A trench (14) subdivides the photodiode layer. A conductor layer (7) is arranged in or at the trench and electrically conductively connects the cathode layer with a cathode connection (11). Anode connections (12) are electrically conductively connected with the anode regions.
    Type: Grant
    Filed: January 24, 2012
    Date of Patent: June 9, 2015
    Assignee: ams AG
    Inventors: Jordi Teva, Franz Schrank
  • Patent number: 9054324
    Abstract: An organic molecular memory of an embodiment includes a first conductive layer, a second conductive layer, and an organic molecular layer interposed between the first conductive layer and the second conductive layer, the organic molecular layer including variable-resistance molecular chains or charge-storage molecular chains, the variable-resistance molecular chains or the charge-storage molecular chains having electron-withdrawing substituents.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: June 9, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideyuki Nishizawa, Shigeki Hattori, Masaya Terai, Satoshi Mikoshiba, Koji Asakawa, Tsukasa Tada
  • Patent number: 9048253
    Abstract: An integrated circuit device and method for manufacturing the integrated circuit device is disclosed. The disclosed method provides improved control over a surface proximity and tip depth of an integrated circuit device. In an embodiment, the method achieves improved control by forming a doped region and a lightly doped source and drain (LDD) region in a source and drain region of the device. The doped region is implanted with a dopant type opposite to the LDD region.
    Type: Grant
    Filed: September 27, 2013
    Date of Patent: June 2, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Feng Nieh, Ming-Huan Tsai, Wei-Han Fan, Yimin Huang, Chun-Fai Cheng, Han-Ting Tsai, Chii-Ming Wu
  • Patent number: 9048445
    Abstract: To provide a gate insulating material which has high chemical resistance, is superior in coatability of a resist and an organic semiconductor coating liquid, and has small hysteresis, a gate insulating film and an FET using the same by a polysiloxane having an epoxy group-containing silane compound as a copolymerization component.
    Type: Grant
    Filed: February 27, 2009
    Date of Patent: June 2, 2015
    Assignee: TORAY INDUSTRIES, INC.
    Inventors: Seiichiro Murase, Takenori Fujiwara, Yukari Jo, Jun Tsukamoto
  • Patent number: 9048123
    Abstract: A semiconductor device includes a first fin rising out of a semiconductor base. It further includes a second fin rising out of the semiconductor base. The second fin is substantially parallel to the first fin that forms a span between the first fin and the second fin. A first dielectric layer is deposited on exposed surfaces of a first gate body area of the first fin, a second gate body area of the second fin, and an adjacent surface of the semiconductor base that defines the span between the first and second gate body areas. A gate electrode layer is sandwiched between the first dielectric layer and a second dielectric layer. The semiconductor device includes a third fin interdigitated between the first fin and the second fin within the span. Exposed surfaces of the gate body area of the third fin are in contact with the second dielectric layer.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: June 2, 2015
    Assignee: International Business Machines Corporation
    Inventors: Karl R. Erickson, Phil C. Paone, David P. Paulsen, John E. Sheets, II, Gregory J. Uhlmann, Kelly L. Williams
  • Patent number: 9040318
    Abstract: There is disclosed a modular lamination approach for processing organic photosensitive devices that allows the individual processing of device components, that once processed are brought together in a final step to make electrical contact. The disclosed method of preparing a laminated photosensitive device having at least one donor-acceptor heterojunction comprises: preparing a top electrode by depositing a functional material on a flexible substrate, such as an elastomer; optionally processing the functional material to obtain desired properties prior to lamination; preparing a bottom portion by depositing a second functional material over a substrate; optionally processing the second functional material to obtain desired properties prior to lamination; and coupling the top electrode to said bottom portion to form a laminated photosensitive device.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: May 26, 2015
    Assignee: The Trustees of Princeton University
    Inventors: Yueh-Lin Loo, Jong Bok Kim
  • Patent number: 9041109
    Abstract: At least one doped semiconductor material region is formed over a crystalline insulator layer. A disposable gate structure and a planarization dielectric layer laterally surrounding the disposable gate structure are formed over the at least one doped semiconductor material region. The disposable gate structure is removed selective to the planarization dielectric layer to form a gate cavity. Portions of the at least one doped semiconductor material region are removed from underneath the gate cavity. Remaining portions of the at least one doped semiconductor material region constitute a source region and a drain region. A channel region is epitaxially grown from a physically exposed surface of the crystalline insulator layer. The channel region has a uniform thickness that can be less than the thickness of the source region and the drain region, and is epitaxially aligned to the crystalline insulator layer.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: May 26, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anirban Basu, Pouya Hashemi, Ali Khakifirooz