Abstract: A method of fabricating an integrated circuit including a first region and a second region each having different poly-silicon gate structures is provided. The method includes depositing a first poly-silicon layer over the first and the second region and depositing, within the second region, an oxide layer over the first poly-silicon layer. A second poly-silicon layer is deposited over the first poly-silicon layer and the oxide region. A portion of the second poly-silicon layer that lies over the oxide region is then stripped away.

Abstract: In a plasma doping device according to the invention, a vacuum chamber is evacuated with a turbo-molecular pump as an exhaust device via a exhaust port while a predetermined gas is being introduced from a gas supply device in order to maintain the inside of the vacuum chamber to a predetermined pressure with a pressure regulating valve. A high-frequency power of 13.56 MHz is supplied by a high-frequency power source to a coil provided in the vicinity of a dielectric window opposed to a sample electrode to generate inductive-coupling plasma in the vacuum chamber. A high-frequency power source for supplying a high-frequency power to the sample electrode is provided. Uniformity of processing is enhanced by driving a gate shutter and covering a through gate.

Abstract: Methods and apparatus provide for: a first source of plasma, wherein the plasma includes a first species of ions; a second source of plasma, wherein the plasma includes a second species of ions; selection of the plasma from the first and second sources; and acceleration the first species of ions or the second species of ions toward a semiconductor wafer.

Abstract: Provided are a light emitting device and a light emitting device package. The light emitting device includes a first electrode, a light emitting structure including a first semiconductor layer, an active layer, and a second semiconductor layer on the first electrode, a second electrode on the light emitting structure, and a reflective member on at least lateral surface of the second electrode.

Abstract: The present invention discloses a micrometer-scale grid structure based on single crystal silicon consists of periphery frame 1 and grid zone 2. The periphery frame 1 is rectangle, and grid zone 2 has a plurality of mesh-holes 3 distributing in the plane of grid zone 2. The present invention also provides a method for manufacturing a micrometer-scale grid structure based on single crystal silicon. According to the present invention thereof, the contradiction between demand of broad deformation space for sensor and actuator and the limit of the thickness of sacrifice layer is solved. Furthermore, the special requirement of double-side transparence for some optical sensor is met.

Abstract: A range image sensor 1 is provided with a semiconductor substrate 1A having a light incident surface 1BK and a surface 1FT opposite to the light incident surface 1BK, a photogate electrode PG, first and second gate electrodes TX1, TX2, first and second semiconductor regions FD1, FD2, and a third semiconductor region SR1. The photogate electrode PG is provided on the surface 1FT. The first and second gate electrodes TX1, TX2 are provided next to the photogate electrode PG. The first and second semiconductor regions FD1, FD2 accumulate respective charges flowing into regions immediately below the respective gate electrodes TX1, TX2. The third semiconductor region SR1 is located away from the first and second semiconductor regions FD1, FD2 and on the light incident surface 1BK side and has the conductivity type opposite to that of the first and second semiconductor regions FD1, FD2.

Abstract: An optoelectronic semiconductor body includes a semiconductor layer sequence which has an active layer suitable for generating electromagnetic radiation, and a first and a second electrical connecting layer. The semiconductor body is provided for emitting electromagnetic radiation from a front side. The first and the second electrical connecting layer are arranged at a rear side opposite the front side and are electrically insulated from one another by means of a separating layer. The first electrical connecting layer, the second electrical connecting layer and the separating layer laterally overlap and a partial region of the second electrical connecting layer extends from the rear side through a breakthrough in the active layer in the direction of the front side. Furthermore, a method for producing such an optoelectronic semiconductor body is specified.

Abstract: A layered chip package includes a main body, and wiring that includes a plurality of wires disposed on a side surface of the main body. The main body includes a plurality of stacked layer portions. A method of manufacturing the layered chip package includes the step of fabricating a layered substructure and the step of cutting the layered substructure. The layered substructure includes: a plurality of arrayed pre-separation main bodies; a plurality of accommodation parts disposed between two adjacent pre-separation main bodies; and a plurality of preliminary wires accommodated in the accommodation parts. The accommodation parts are formed in a photosensitive resin layer by photolithography. In the step of cutting the layered substructure, the plurality of pre-separation main bodies are separated from each other, and the wires are formed by the preliminary wires.

Abstract: Provided is a crack-free epitaxial substrate having excellent breakdown voltage properties in which a silicon substrate is used as a base substrate thereof. The epitaxial substrate includes: a (111) single crystal Si substrate and a buffer layer including a plurality of composition modulation layers each formed of a first composition layer made of AlN and a second composition layer made of AlxGa1-xN (0?x<1) being alternately laminated. The relationship of x(1)?x(2)? . . . ?x(n?1)?x(n) and x(1)>x(n) is satisfied, where n represents the number of laminations of each of the first and the second composition layer, and x(i) represents the value of x in i-th one of the second composition layers as counted from the base substrate side. Each of the second composition layers is formed so as to be in a coherent state relative to the first composition layer.

Abstract: A process of manufacturing a crystalline silicon solar cell includes forming a rough surface on a surface of the crystalline silicon wafer and an Al2O3 film is coated on a non-rough surface thereof. A single-sided n diffusion layer and phosphosilicate glass film are formed. An anti-reflection layer SiNx film is formed on a top surface of the phosphosilicate glass film. An Al metallic film is formed as a back ohmic electrode on the Al2O3 film. The local area of the anti-reflection layer SiNx film and the phosphosilicate glass film is melted and removed to form a local area of n+-Si layer. Then, an Al—Si back ohmic contact electrode is formed between the Al metallic film and the crystalline silicon wafer. A front ohmic contact electrode is formed on the molten and removed area of the antireflection layer SiNx film and the phosphosilicate film by light-induced plating.

Abstract: Generally, the present disclosure is directed to various methods of making a semiconductor device by implanting hydrogen or hydrogen-containing clusters to improve the interface between a gate insulation layer and the substrate. One illustrative method disclosed herein involves forming a gate insulation layer on a substrate, forming a layer of gate electrode material above the gate insulation material and performing an ion implantation process with a material comprising hydrogen or a hydrogen-containing compound to introduce the hydrogen or hydrogen-containing compound proximate an interface between the gate insulation layer and said substrate with a concentration of the implanted hydrogen or hydrogen-containing compound being at least 1e10 ions/cm2.

Abstract: Wafer-scale packaging structures and methods are provided for integrally packaging antenna structures with semiconductor RFIC (radio frequency integrated circuit) chips to form compact integrated radio/wireless communications systems for millimeter wave (mmWave) and Terahertz (THz) applications. For example, a chip package includes an RFIC chip, an antenna structure and an interface layer. The RFIC chip includes a semiconductor substrate having an active surface and an inactive surface, and a BEOL (back end of line) structure formed on the active surface of the semiconductor substrate. The antenna structure includes an antenna substrate and a planar antenna radiator formed on a surface of the antenna substrate, wherein the antenna substrate is formed of a low loss semiconductor material. The interface layer connects the antenna structure to the BEOL structure of the RFIC chip.

Abstract: An LED unit includes an LED and an electrochromic element mounted on the LED. The LED includes a base, a light emitting die mounted on the base, a pair of leads electrically connected to the die and an encapsulant sealing the die. The encapsulant has a first area and a second area around the first area. The first area contains yellow phosphor therein, and the second area contains red phosphor therein. The electrochromic element has an opening through which the first area of the encapsulant is exposed. The second area of the encapsulant is covered by the electrochromic element. The electrochromic element can change its color when being electrified, thereby changing the color temperature of the light output from the LED unit.

Abstract: A method for forming a DRAM MIM capacitor stack comprises forming a first electrode layer, annealing the first electrode layer, forming a dielectric layer on the first electrode layer, annealing the dielectric layer, forming a second electrode layer on the dielectric layer, annealing the second electrode layer, patterning the capacitor stack, and annealing the capacitor stack for times greater than about 10 minutes, and advantageously greater than about 1 hour, at low temperatures (less than about 300 C) in an atmosphere containing less than about 25% oxygen and preferably less than about 10% oxygen.

Abstract: A plurality of metal patterns are disposed on a substrate. A support structure is provided between the plurality of metal patterns. The support structure has a supporter and a glue layer. Each of the plurality of metal patterns has a greater vertical length than a horizontal length on the substrate when viewed from a cross-sectional view. The supporter has a band gap energy of at least 4.5 eV. The glue layer is in contact with the plurality of metal patterns. The supporter and the glue layer are formed of different materials.

Abstract: A laser ablation nozzle including a main pressure chamber centered on an area of a substrate to be ablated and arranged to push a stream of gas through the main pressure chamber onto the substrate. A vacuum chamber surrounds the main pressure chamber and is arranged to vacuum away the process gas and ablation debris. To attempt to address uneven pressure and flow, flow restrictors can be provided at one or both of the process gas inlet and the vacuum chamber. The vacuum flow restrictor is intended to create constriction in a channel to generate a uniform vacuum induced flow around substantially the entire circumference of the nozzle opening. Similarly, the process gas flow restrictor is intended to generate substantially uniform gas flow into the main pressure chamber.

Abstract: A method for fabricating a group-III nitride semiconductor laser device having a semi-polar surface provides a laser cavity mirror which can reduce lasing threshold current. A support plate H tilts at an angle THETA from an m-axis toward a reference plane Ab defined by a direction PR of travel of the blade 5g and an a-axis in a c-m plane while the direction PR is being orthogonal to the front surface Ha of the support plate H. The blade 5g is positioned so as to be aligned to a plane which includes an intersection P1 between the endmost scribe mark 5b1 among a plurality of scribe marks 5b and the front surface 5a of the substrate product 5 and extends along the direction PR. In the case where the angle ALPHA defined ranges either from 71 to 79 degrees or from 101 to 109 degrees, the angle THETA then ranges from 11 to 19 degrees, and thereby the reference plane Ab along the direction PR extends along the c-plane orthogonal to the c-axis.

Abstract: Disclosed is a light emitting device including a substrate, a light emitting structure arranged on the substrate, the light emitting structure including a first semiconductor layer, a second semiconductor layer and an active layer arranged between the first semiconductor layer and the second semiconductor layer, a first electrode electrically connected to the first semiconductor layer, and a second electrode electrically connected to the second semiconductor layer, wherein the light emitting structure has a top surface including a first side and a second side which face each other, and a third side and a fourth side which face each other.

Abstract: A method of forming, on a surface of a substrate, at least one hydrophilic attachment area for the purpose of self-assembling a component or a chip, in which a hydrophobic area, which delimits the hydrophilic attachment area, is produced.

Abstract: A power semiconductor device includes: a mold unit that includes a power semiconductor element, a base plate, and a mold unit, the power semiconductor element being mounted on one surface of the base plate, a convex portion being formed on an other surface of the base plate, the convex portion including a plurality of grooves, the mold unit having a mold resin with which the power semiconductor element is sealed in such a manner as to expose the convex portion; a plurality of radiation fins inserted into the grooves, respectively, and fixedly attached to the base plate by swaging; and a metal plate that includes a opening into which the convex portion is inserted, the metal plate being arranged between the mold unit and the radiation fins with the convex portion inserted into the opening, wherein the metal plate includes a protrusion that protrudes from an edge of the opening and that digs into a side surface of the convex portion when the convex portion is inserted into the opening.