Abstract: A semiconductor device is formed in a semiconductor substrate comprising a first main surface and includes a control gate disposed in a lower portion of a first trench formed in the first main surface, a floating gate disposed in the first trench above the control gate and insulated from the control gate, a source region of a first conductivity type, a body region of a second conductivity type, and a drain region of the first conductivity type.

Abstract: In a transistor including an oxide semiconductor film, a metal oxide film which has a function of preventing electrification and covers a source electrode and a drain electrode is formed in contact with the oxide semiconductor film, and then, heat treatment is performed. Through the heat treatment, impurities such as hydrogen, moisture, a hydroxyl group, or hydride are intentionally removed from the oxide semiconductor film, whereby the oxide semiconductor film is highly purified. By providing the metal oxide film, generation of a parasitic channel on the back channel side of the oxide semiconductor film in the transistor can be prevented.

Abstract: A field effect transistor including a source electrode 107a, a drain electrode 107b, a gate electrode 103, an insulating film 105 and a semiconductor layer 109 containing a crystalline oxide, wherein the source electrode 107a and the drain electrode 107b are self-aligned with the gate electrode 103 with the insulating film 105 therebetween.

Abstract: A memory device includes a first metal layer and a first metal oxide layer coupled to the first metal layer. The memory device includes a second metal oxide layer coupled to the first metal oxide layer and a second metal layer coupled to the second metal oxide layer. The formation of the first metal oxide layer has a Gibbs free energy that is lower than the Gibbs free energy for the formation of the second metal oxide layer.

Abstract: Methods of manufacturing a semiconductor device are provided. Patterns having a recess region defined therebetween are formed on a substrate, and then a silicon precursor having an organic ligand is provided on the substrate to absorb silicon on sidewalls and a bottom surface of the recess region to form a silicon monolayer on the patterns having the recess region defined therebetween. A silicon layer without void and cutting is formed on the silicon monolayer.

Abstract: Disclosed are a light emitting device. A light emitting diode comprises a light emitting device comprises a plurality of N-type semiconductor layers including a first N-type semiconductor layer and a second N-type semiconductor layer on the first N-type semiconductor layer, an active layer on the second N-type semiconductor layer, and a P-type semiconductor layer on the active layer, wherein the first N-type semiconductor layer comprises a Si doped Nitride layer and the second N-type semiconductor layer comprises a Si doped Nitride layer, and wherein the first and second N-type semiconductor layers have a Si impurity concentration different from each other.

Abstract: An embodiment of the invention provides an interposer which includes: a substrate having a first surface and a second surface; a first hole extending from the first surface towards the second surface; a second hole extending from the first surface towards the second surface, wherein a width of the first hole is different from a width of the second hole; an insulating layer located on the substrate and extending onto a sidewall of the first hole and a sidewall of the second hole; and a conducting layer located on the insulating layer on the substrate and extending onto the sidewall of the first hole, wherein there is substantially no conducting layer in the second hole.

Abstract: A method of fabricating a semiconductor integrated circuit (IC) is disclosed. The method includes receiving a semiconductor device, patterning a first hard mask to form a first recess in a high-resistor (Hi-R) stack, removing the first hard mask, forming a second recess in the Hi-R stack, forming a second hard mask in the second recess in the Hi-R stack. A HR can then be formed in the semiconductor substrate by the second hard mask and a gate trench etch.

Abstract: Mirror-polished CZ wafer and FZ wafer are prepared. A first impurity region which will be a first isolation region is formed in a surface layer of a first main surface of the CZ wafer. The first main surface of the CZ wafer and a first main surface of the FZ wafer are bonded to each other by an inter-molecular bond. A second impurity region which will be a second isolation region is formed in a surface layer of a second main surface of the FZ wafer. A heat treatment is performed to diffuse the first impurity region and the second impurity region such that the first impurity region and the second impurity region are continuous, thereby forming a through silicon isolation region.

Abstract: A reduction in contaminating impurities in a TFT, and a TFT which is reliable, is obtained in a semiconductor device which uses the TFT. By removing contaminating impurities residing in a film interface of the TFT using a solution containing fluorine, a reliable TFT can be obtained.

Abstract: A compliant monopolar micro device transfer head array and method of forming a compliant monopolar micro device transfer array from an SOI substrate are described. In an embodiment, the micro device transfer head array including a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include a silicon interconnect and an array of silicon electrodes electrically connected with the silicon interconnect. Each silicon electrode includes a mesa structure protruding above the silicon interconnect, and each silicon electrode is deflectable into a cavity between the base substrate and the silicon electrode. A dielectric layer covers a top surface of each mesa structure.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device including forming a first SiGe layer on an insulating film, processing the first SiGe layer to have an island shape which includes a first region and a second region, the first region having a width larger than a width of the second region in a direction perpendicular to a connecting direction of the second region, subjecting the first SiGe layer having the island shape to thermal oxidation, thereby increasing Ge composition of the first and second region, and setting the Ge composition of the second region to be higher than the Ge composition of the first region, melting the second region having the increased Ge composition by heat treatment, and recrystallizing the melted second region from an interface between the first and second region.

Abstract: According to one embodiment, a memory device includes a nanomaterial assembly layer, a first electrode layer and a second electrode layer. The nanomaterial assembly layer is formed of an assembly of a plurality of micro conductors via gaps between the micro conductors. The first electrode layer is provided on the nanomaterial assembly layer. The second electrode layer is provided on the first electrode layer.

Abstract: A semiconductor device comprising a substrate having a transistor that includes a metal gate structure; a first oxide layer formed over the substrate; a silane layer formed on the first oxide layer; and a non-conductive metal oxide layer grown on the metal gate structure, wherein the silane layer inhibits nucleation and growth of the non-conductive metal oxide layer.

Abstract: Disclosed herein is a light emitting device including a light emitting structure including a first conductivity-type semiconductor layer, a second conductivity-type semiconductor layer, and an active layer including at least one combination of a well layer of a first composition formed of a nitride-semiconductor material having first electronic energy and a barrier layer of a second composition formed of a nitride-semiconductor material having higher electronic energy than the first electronic energy, and an interface layer disposed between the second conductivity-type semiconductor layer and the active layer or between the first conductivity-type semiconductor layer and the active layer. The interface layer includes first, second and third layers having different energy bandgaps, the energy bandgaps of the first and second layers are greater than the energy bandgap of the barrier layer, and the energy bandgap of the third layer is less than the energy bandgap of the barrier layer.

Abstract: Non-planar semiconductor FET based sensors are provided that have an enhanced sensing area to volume ratio which results in faster response times than existing planar FET based sensors. The FET based sensors of the present disclosure include a V-shaped gate dielectric portion located in a V-shaped opening formed in a semiconductor substrate. In some embodiments, the FET based sensors of the present disclosure also include a self-aligned source region and a self-aligned drain region located in the semiconductor substrate and on opposing sides of the V-shaped opening. In other embodiments, the FET based sensors include a self-aligned source region and a self-aligned drain region located in the semiconductor substrate and on opposing sides of a gate dielectric material portion that is present on an uppermost surface of the semiconductor substrate.

Abstract: In some embodiments, the present invention discloses plasma processing at interfaces of an ALD metal oxide film with top and bottom electrodes to improve the ReRAM device characteristics. The interface processing can comprise an oxygen inhibitor step with a bottom polysilicon electrode to prevent oxidation of the polysilicon layer, enhancing the electrical contact of the metal oxide film with the polysilicon electrode. The interface processing can comprise an oxygen enrichment step with a top metal electrode to increase the resistivity of the metal oxide layer, providing an integrated current limiter layer.

Abstract: A method of manufacturing a semiconductor device includes supplying a process gas into a process vessel accommodating a substrate to form a thin film on the substrate and supplying a cleaning gas into the process vessel to clean an inside of the process vessel, after the supplying the process gas to form the thin film is performed a predetermined number of times. When cleaning the inside of the process vessel, a fluorine-containing gas, an oxygen-containing gas and a hydrogen-containing gas are supplied as the cleaning gas into the process vessel heated and kept at a pressure less than an atmospheric pressure to remove a deposit including the thin film adhering to the inside of the process vessel through a thermochemical reaction.

Abstract: Alignment tolerances between narrow mask lines, for forming interconnects in the array region of an integrated circuit, and wider mask lines, for forming interconnects in the periphery of the integrated circuit, are increased. The narrow mask lines are formed by pitch multiplication and the wider mask lines are formed by photolithography. The wider mask lines and are aligned so that one side of those lines is flush with or inset from a corresponding side of the narrow lines. Being wider, the opposite sides of the wider mask lines protrude beyond the corresponding opposite sides of the narrow mask lines. The wider mask lines are formed in negative photoresist having a height less than the height of the narrow mask lines. Advantageously, the narrow mask lines can prevent expansion of the mask lines in one direction, thus increasing alignment tolerances in that direction.

Abstract: A method for manufacturing an array substrate of a transflective LCD includes: (1) providing a substrate; (2) forming a transparent electrode layer on the substrate and forming a first metal layer on the transparent electrode layer; (3) applying a first photo-masking operation to form a gate terminal and a pixel electrode; (4) forming an insulation layer on the gate terminal and the pixel electrode; (5) applying a second photo-masking operation to form a gate insulation layer on the insulation layer; (6) forming a semiconductor layer on the gate insulation layer and forming a second metal layer on the semiconductor layer and the pixel electrode; and (7) applying a third photo-masking operation to form a channel layer on the semiconductor layer and also forming a drain terminal, a source terminal, and a reflector section on the second metal layer, so as to form a thin-film transistor.