Abstract: A new semiconductor memory device for performing a read/write of information of randomly accessed address includes a plurality of memory cells put in parallel arrays. Each memory cell includes a switching transistor region and a capacitor region. The capacitor regions of the two adjacent memory cells are formed in a common region over the switching transistor region of the two adjacent memory cells. The charge storage electrode of the capacitor region has the shape of a loop. The charge storage electrodes are formed by using self-alignment.

Abstract: A MOSFET Static Random Access Memory (SRAM) cell has a symmetrical construction, with a pair of word lines. The word lines are in second level polysilicon, so that they may overlap the driving transistor gates which are in first level polysilicon.

Abstract: A master-slice type semiconductor integrated circuit device of the invention has a master substrate and a plurality of basic cells provided on the master substrate. Each of the basic cells includes a plurality of resistors and a plurality of transistors. A plurality of wirings are provided in the master substrate to form a predetermined logic circuit. The wirings in each of the basic cells are changed such that the current to flow in each transistor may be selected in a number of ways without the logical amplitude being changed in the logical circuit.

Abstract: A circuit for generating a negative voltage includes: a bipolar transistor including, a) an N type collector region, b) a P type base region, and c) an N type emitter region, the base region width between the emitter region and the collector region being less than about 5,000 angstroms and the dopant concentration of the base region being in the range of about 1-10.times.10.sup.18 atoms/cm.sup.3 ; means for applying a reference potential to the base region; and means for applying a bias potential to the emitter region so as to generate a negative output potential at the collector region. The circuit can likewise comprise a PNP bipolar transistor biased to generate a negative voltage. The circuit can be used on integrated circuit chips to provide a complementary voltage, thereby obviating the requirement for separate, complementary power supplies.

Abstract: A packaging structure is provided which is especially useful for solid-state imaging devices and other semiconductor devices. An Al film is selectively formed on inner lead portions and portions of positioning reference plates located within a ceramic packaging body. On the other hand, the outer lead portions that are exposed outside the packaging body are coated with Sn plating layer. Particular care is taken not to locate the Sn plating layer over the Al film. Contamination faults due to Sn swelling and stripping are prevented, while bonding strength of the Al clad inner lead portions with Al internal fine wires and with fit glass joining the ceramic packaging body together is kept high.

Abstract: A first device region (10) of one conductivity type adjacent one major surface (1a) of a semiconductor body (1) has a relatively highly doped subsidiary region (11) spaced from the one major surface (1a) by a relatively lowly doped subsidiary region (12). A second device region (20) of the opposite conductivity type within the subsidiary region (12) has an intrinsic subsidiary region (21) and an extrinsic subsidiary region (23,24) surrounding the intrinsic subsidiary region (21) forming respective first and second pn junctions (22,25) with the relatively lowly doped subsidiary region (12). A third device region (30) of the one conductivity type is formed within the intrinsic subsidiary region (21) surface (1a).

Abstract: A dynamic random access memory (DRAM) is disclosed that can effectively prevent the formation of steps in the boundary region of a memory cell array 101 and a peripheral circuit 102, even in high integrated devices. This DRAM includes a double peripheral wall 20 of peripheral walls 20a and 20b at the boundary region of the memory cell array 101 and the peripheral circuit 102 of a P type silicon substrate 1, extending vertically upwards from the P type silicon substrate 1. The upper surfaces of the devices formed on the memory cell array and the peripheral circuit 102 in forming devices on the memory cell array 101 and the peripheral circuit 102 are substantially planarized, by virture of the double peripheral wall 20, to effectively prevent steps from being generated in the boundary region of the memory cell array 101 and the peripheral circuit 102, even in high integrated devices.

Abstract: A thin film of SiO.sub.2 is patterned on an N layer consisting of N-type Al.sub.x Ga.sub.1-x N (inclusive of x=0). Next, I-type Al.sub.x Ga.sub.1-x N (inclusive of x=0) is selectively grown and the portion on the N layer grows into an I-layer consisting an active layer of a light emitting diode, and that on the SiO.sub.2 thin film grows into a conductive layer. Electrodes are formed on the I-layer and conductive layer to constitute the light emitting diode. Also, on the surface a ({1120}) of a sapphire substrate, a buffer layer consisting of aluminum nitride is formed, onto which a gallium nitride group semiconductor is formed.

Abstract: A solid-state CCD imaging device has a substrate, photosensitive pixel cells provided as pixel sections in the substrate, and a transfer section, provided in the substrate, for transferring signal charge carriers read out from the pixel cells in a predetermined transfer direction. The transfer section has a semiconductive charge transfer channel layer formed in the substrate and transfer electrodes insulatively provided above the substrate and arrayed in the above direction while predetermined gap sections are kept therebetween. Each of the transfer electrodes defines one charge transfer stage. A gap potential control electrode layer is insulatively disposed above the electrodes.

Abstract: Disclosed are novel fast semiconductor photodetector means that comprise a good asymmetric superlattice structure. Associated with the material of the structure is a relatively short minority carrier effective lifetime .tau..sub.e, typically .tau..sub.e <10.sup.-9 sec. In response to a constant photon flux of appropriate wavelength the photodetector can have a substantially constant voltage output that is proportional to the photon flux for small values of flux, and that saturates at a value that is substantially proportional to .tau..sub.e.sup.-1 for relatively large values of flux. The novel photodetector means can be advantageously combined with a FET or bipolar transistor, and the combination can be part of an integrated circuit.

Abstract: A charge transfer device has a plurality of registers which run parallel to each other and across which electrical charges are transferred. For efficient charge transfer across the registers, the transfer elecrtrode of one register and the transfer electrode of an adjacent register are arrayed in contiguity to each other and driven by different driving pulses and a deeper potential is provided in the signal charge receiving side than in the signal charge forwarding side. The registers are arrayed parallel to a sensor row constituted by a linear array of different color sensors and each handle signal charges of the respective colors. In this manner, the outputs from the registers are in the form of the separate color signals to prevent color mixing.

Abstract: A semiconductor device is provided of the type having a doped semiconductor region coupled to source and drain electrodes and an elongated control gate contacting the doped region along the length of the gate for forming a nonconducting depletion region across the doped region for preventing current flow therethrough with the gate having a minimized width to reduce contact area with the doped region, wherein the width of the gate is repeatedly reduced along the length thereof for further reducing contact area with the doped semiconductor region.

Abstract: A thin-film transistor basically comprises an insulating substrate, a gate electrode formed on the substrate, a gate insulating layer covering the gate electrode, a semiconductor layer formed on the gate insulating layer, and source/drain electrodes electrically connected to the semiconductor layer. An insulating layer is interposed between the source/drain electrodes and the semiconductor layer, and the source/drain electrodes are electrically connected to the semiconductor layer through a pair of openings provided in the insulating layer. The connection to the semiconductor layer is made directly or via an electrical connection member.

Abstract: A semiconductor layer made of an epitaxial growing layer (16) is formed on the surface of a p.sup.- -type silicon semiconductor substrate (11), first impurity regions are formed by p.sup.+ -type buried regions (171, 172) and a p-type impurity regions (221, 222) throughout the semiconductor layer from its surface to the semiconductor substrate so as to divide said semiconductor layer into side element regions (161, 162) and a central island region (163). An anode layer obtained by alternately arranging n.sup.+ -type impurity regions (251 to 253) and p.sup.+ -type impurity regions (231, 232) is formed in surface regions of the pair of impurity regions, and cathode regions made of p-type impurity regions (231, 232) are formed in the element regions of the semiconductor layer. Gate electrodes are formed to be opposite to each other through a gate insulating film in p-n junction portions constituted by the n.sup.+ -type impurity regions (251, 252) the p-type impurity regions (221, 222), and an n.sup.

Abstract: The BiMOS devices are compact 3D devices having a coupled bipolar and MOS mechanisms integrated in one single cell. The gates cover over the bipolar regions. The bipolar regions are the tubs of the MOS mechanisms. The MOS mechanisms make the connection between the base, emitter and collector to charge and discharge the base voltage. The input applies on the gate to switch on/off the base current of the bipolar mechanism. There are P-PNP, N-NPN, N-PNP, P-NPN, PN-PNP, PN-NPN, NP-PNP and NP-NPN BiMOS devices. The BiMOS inverter, NOR, NAND logic gates are the single stage circuit having the same circuit configuration as CMOS circuits. They are made of P-PNP, N-NPN, NP-PNP and NP-NPN BiMOS devices. The digital BiMOS buffer, OR, AND logic gates are the single stage circuits made of N-PNP, P-NPN, PN-PNP and PN-NPN BiMOS devices. Furthermore, the BiMOS technologies are applied to SRAM, EPROM and EEPROM to generate the BiMOS SRAM, BiMOS EPROM and BiMOS EEPROM memory devices.

Abstract: In a memory cell of SRAM of CMOS type, load MISFET having a polycrystalline silicon film as area of source, drain and channel is stacked on drive MISFET, and gate electrodes of the drive MISFET and the load MISFET are constituted by conductive films in different layers. Area of source and drain provided on the polycrystalline silicon film has an overlapped area with the gate electrode of the load MISFET.

Abstract: A resin sealed semiconductor device includes a semiconductor chip formed on a substrate and sealed with resin. A concave portion is formed on a major surface of a semiconductor substrate between an insulating film for isolation and an edge of the major surface of the semiconductor substrate. This concave portion is filled with a buffer member having an elastic modulus smaller than that of the material of the semiconductor substrate. Mechanical stress applied to an edge of the semiconductor substrate, caused by the callosity of resin, is absorbed and reduced by the buffer member. A portion of the semiconductor substrate between the concave portion and the insulating film for isolation prevents the remainder of the mechanical stress from being transmitted from the buffer member to the insulating film and circuit elements.

Abstract: Field-effect transistor devices are provided having a relatively substantial capability to withstand reverse bias voltages. This capability is provided through providing shields in these devices near junctions in such devices which are subject to breakdown under large reverse bias voltages, those shields being operable at selected voltages. The device can also be provided having a relatively low "on" condition resistance between the source and drain terminals thereof by virtue of a geometrical design choice. A method for fabricating one such device is also disclosed.

Abstract: An arrangement for interconnecting high density signals of integrated circuits includes an electronic circuit on a multilayered substrate which includes at least three layers. These layers comprise a signal layer for carrying signals in the electronic circuit, a dielectric layer of organic material disposed adjacent the signal layer, and a metallic reference layer. The layers are disposed such that the dielectric layer is between the signal layer and the metallic reference layer. For providing controlled line impedance and for reducing cross-talk between the signals carried in the electronic circuit, the metallic reference layer includes uniformly spaced apertures which are situated in a slanted grid arrangement.

Abstract: An integrated circuit having a first group of semiconductor components which use potentials which are positive with respect to the substrate and a second group of components which use potentials which are negative with respect to the substrate. A negative voltage regulator circuit suitable for use in telephone circuits is described in which the regulated output is produced at the substrate so that noise can be prevented from being capacitatively coupled from the substrate to the input stages of amplifiers in the same integrated circuit. The exemplary circuit is produced by the so-called BIDFET process and use both bipolar and field effect transistors.