Abstract: The EEPROM has the selection device in series with the memory device having a floating gate disposed over the channel between the buried drain and the buried source, and insulated from the channel by 200 A to 1000 A of gate oxide, an add-on floating gate shorted electrically to the floating gate, and disposed over and insulated from the buried drain by 40 A to 150 A of tunnel dielectric, and a control gate disposed over and insulated from the floating gate. The improvement in the proposed version of the memory device in the EEPROM is that the tunnel dielectric area is very small and is self aligned to the floating gate.

Abstract: The device for shielding the electrons injected towards the substrate by an epitaxial pocket which reaches a negative voltage with respect to said substrate, comprises a debiasing transistor arranged in reverse configuration (with collector and emitter swapped) in the same epitaxial pocket reaching a negative voltage. The transistor is connected with its emitter and its collector between the buried layer of the pocket reaching a negative voltage and the substrate, so as to debias the junction formed by the buried layer and the substrate.

Abstract: An ESD protection device is formed in an integrated circuit by an N-channel grounded-gate transistor. This protection device has a polysilicon gate, just as other P- and N-channel transistors in the integrated circuit device, but the siliciding of the protection device is controlled so that adverse effects of ESD events are minimized. There are no silicide areas created on top of the polysilicon gate of the protection device, nor on the source/drain regions near the gate and self-aligned with the gate, as there is for other transistors made by the CMOS process. The siliciding of the protection transistor near the gate is prevented by using a deposited oxide layer as a mask, and this oxide layer is also used to create sidewall spacers for the transistor gates. The sidewall spacers are used in creating self-aligned silicided areas over the source/drain regions, self-aligned with the gates, for all P- and N-channel transistors except the protection transistors.

Abstract: A DRAM having the capacitors of memory cells formed by utilizing moats is disclosed. The moats are provided in a semiconductor substrate independently for the respective capacitors by anistropic dry etching, and they serve to increase the capacitances of the capacitors without increasing the areas which they occupy. The greater part of each capacitor is buried in the moat. The capacitors are electrically isolated from the semiconductor substrate, and the semiconductor substrate is not used as the electrodes of the capacitors. The capacitor consists of first and second polycrystalline silicon layers, and an insulator film formed therebetween. The first polycrystalline silicon layer serves as a lower electrode electrically isolated from the semiconductor substrate. This first polycrystalline silicon layer is formed independently for each capacitor, and it is connected to the source or drain region of the MISFET of the memory cell.

Abstract: The flash EEPROM memory device with the floating gate that is over the channel area and insulated from the channel by 200 to 1000 A of gate oxide, and that is also over the thin tunnel dielectric area at the source and insulated from the source by 70 A to 200 A of tunnel dielectric. Another improvement of the proposed version of the flash EEPROM memory device is that the tunnel dielectric area is small and self aligned to the floating gate.

Abstract: A semiconductor-based radiation-detector element particularly adapted to neutron detection, and the method for making the same, in which a high sensitivity single-crystal semiconductor substrate has diffused therein at-least-one region of .sup.3 He gas, which remains resident therein, whereby, upon application of an inverse bias to the junction in the semiconductor substrate, the colliding of incident neutrons with the resident .sup.3 He gas results in a reaction which produces hole-electron pairs in the depletion layer within the semiconductor, those hole-electron pairs producing output electrical pulses which appear at the output terminals of the detector for utilization by detection and measuring apparatus connected to the semiconductor-based radiation-detector element.

Abstract: One embodiment of the present invention provides an EPROM array having floating gate field effect transistors formed on the sidewalls of trenches formed in a semiconducting substrate. Simultaneous with the fabrication of these trench wall transistors, column lines are formed between the trenches to the top surface in the bottom of the trenches which extend from one end to the other of the memory array.

Abstract: The invention relates to an integrated circuit having a transistor suitable for integrated injection logic (I.sup.2 L) with a single collector output region and having at least one base contact disposed between the collector output region (C.sub.60, C'.sub.60) and the injector (IN.sub.6), the surface of the collector output region being several times larger than that of a logic gate of the I.sup.2 L multi-collector type. The base (B.sub.60) has at least two rows of interconnected contacts: a first row (CB.sub.60, CB.sub.61, CB.sub.62) constituting the base contact disposed between the collector and the injector, and at least a second row (CB.sub.63, CB.sub.64, CB.sub.65) situated at the perimeter of the collector (C.sub.60,C'.sub.60), which can consist of one or several parts. The injector (IN.sub.6) may also have a row of interconnected contacts (CIN.sub.1, CIN.sub.2, CIN.sub.3).

Abstract: A plurality of discrete bonding sites on an integrated circuit chip are electrically interconnected using a unique electrical interconnection lead. The interconnection lead comprises an electrically conductive strip having a first end and a second end. The strip is integrally connected at its first end to an electrically conductive tape comprising a plurality of conductive strips. The interconnection lead further comprises a plurality of bonding regions provided between the first and second ends of the conductive strip. These bonding regions provide the sites wherein the conductive strip is electrically connected to the appropriate bond site on the chip. The interconnection lead is suitable for use with tape automated bonding and flexible circuitry techniques.

Abstract: A transistor structure is disclosed which has a vertical channel which has its length controllable by currently-used diffusion processes, and which occupies a minimum of silicon surface area. The transistor is constructed by using a triple-level implant and diffusion process. The drain region is diffused into the silicon area by way of ion implantation and subsequent diffusion. The channel region, of opposite conductivity-type from the drain region, is implanted and diffused into the drain region. The source region is similarly implanted, and diffused into the channel region. A trench is etched into the silicon, extending through the source, channel and drain regions; gate oxide is grown in the trench and a polysilicon gate is deposited in the trench, conformal with the gate oxide. Transistor action takes place in the channel region along the walls of the trench, dependent upon the voltage applied to the gate electrode.

Abstract: An electrically erasable, progammable, read-only-memory, floating-gate, metal-oxide-semiconductor transistor constructed in a trench extending through layers of P-type and N-type material formed on a semiconductor substrate. The floating-gate transistor is comprised of two source-drain regions, a channel region, a floating gate, a programming gate, and gate-oxide layers and is characterized by a floating-gate to channel capacitance that is small relative to the programming-gate to floating-gate capacitance, thereby allowing charging of the floating gate using programming and erasing voltages of less magnitude than might otherwise be necessary.

Abstract: The invention concerns pre-implanted circuits in a rapid semiconductor such as GaAs, comprising a network of cells formed of active and passive components. The cells are supplied but are not interconnected between one another. The interconnection between the cells is made by capacitive or magnetic coupling between two metallization levels separated by an insulating layer. Between a component of a first cell and a component of a second cell, both pre-implanted in a substrate, the interconnection made by means of microstrips supported by the substrate and in ohmic contact with the said components and microstrips supported by an insulating layer, microstrips and insulator forming capacities in the zones where there is covering.

Abstract: A thermoelectrically cooled integrated circuit package is provided which includes a thermally conductive dielectric substrate, an input connecting portion and an output connecting portion supported by the dielectric substrate, and an integrated circuit chip including an input terminal and output terminal. The input terminal is electrically connected to the input connecting portion via a first conductive material, and the output terminal is electrically connected to the output connecting portion via a second conductive material. The first conductive material and the second conductive material thermoelectrically cool the integrated circuit chip when a signal passes through the first conductive material and the second conductive material.

Abstract: On a film to be etched by the isotropic etching method to form electrodes, wiring layers or the like, a first mask and a second mask are provided. The first mask is used for forming the electrodes, wiring layers or the like. The second mask is used for forming a checking pattern from the film to determine the progress of etching. The second mask comprises a plurality of straight lines of different widths and at least one mark pattern indicating one of the straight lines. Upon progress of the isotropic etching, parts of the film under the narrowest and narrower straight lines of the second mask are completely etched by side etching phenomenon which proceeds under the mask with parts of the film under wider straight lines being survived. The mark of the film transferred from the mark pattern of the second mask indicates the position under a predetrmined one of the straight lines of the second mask.

Abstract: A semiconductor device having a grooved field plate(s), a grooved field limiting ring(s) or a combination of a grooved field plate(s) and grooved field limiting ring(s) is disclosed. The grooved modification of the conventional semiconductor results in an increased break-down voltage over the conventional semiconductor device. A method for manufacturing the grooved semiconductor device is disclosed.

Abstract: A Schottky barrier CCD infra-red (IR) detector array having Schottky junction IR sensitive gates as the transfer gates of the CCD array. These Schottky gates perform both IR detection and CCD shift register function within the array, thereby improving the fill factor and/or pixel size of the device.

Abstract: A structure and method for making a pair of MOS field effect transistors (MOSFETs), one stacked upon the other in an integrated circuit device is disclosed. In one embodiment of the device, the active layer of the upper MOSFET is epitaxially grown from an exposed surface of the active layer of the lower MOSFET. In another embodiment, the active layer of the upper MOSFET is polysilicon which, optionally, may be recrystallized. In all embodiments, the pair of MOSFETs share a common gate.

Abstract: In a semiconductor device including a substrate of Si or polycrystalline silicon and an interlayer insulation film region, a region for interconnection with the substrate is composed of a refractory metal silicide layer, a refractory metal nitride layer, an Al or Al alloy layer, and possibly a further refractory metal nitride layer, while a region for interconnection on the interlayer insulation film on the substrate is composed of a refractory metal, or refractory metal oxide layer, a refractory metal nitride layer, an Al or Al alloy layer, and possibly a further refractory metal nitride layer, providing interconnections for integrated circuits. In the manufacture of this interconnection structure, rapid thermal annealing is performed at 600.degree.-1000.degree. C. on the refractory metal nitride layer of the region for interconnection with the substrate, followed by the formation of Al or Al alloy layer.

Abstract: A test structure for measuring bipolar transistor gain has a base contacting region (16) doped the same conductivity type as the emitter region (13). The base contacting region (16) is located within a region (15) overlapping with and more heavily doped than the transistor base (12). Polysilicon contacts 21, 22 are provided respectively to the transistor emitter 13 and to the base contacting region 16.

Abstract: A multiplicity of field effect type semiconductor memory elements are formed perpendicular to a surface of a semiconductor wafer. Charge carriers are transported in the semiconductor bulk perpendicular to the surface and a potential barrier is formed in the current path to accomplish storing. Since the bulk mobility of a semiconductor is far larger than the surface mobility, the transit time of the carriers is much improved. Furthermore, since each structure of the memory cells is formed perpendicular to the semiconductor surface, the surface occupation area per memory cell is reduced. Thus, a high-speed and high-density semiconductor memory device is provided.