Abstract: A storage controller includes a prefetch buffer configured to buffer data prefetched from a non-volatile memory during a prefetch operation, a determiner circuit configured to output one of the prefetched data and normal data read from the non-volatile memory, as read data, and a prefetch control circuit configured to enable the prefetch operation during a first time when a sequential read operation is performed on the non-volatile memory, disable the prefetch operation at a second point after the first time, and enable the prefetch operation or maintain the disable of the prefetch operation according to performance of the read data in a prefetch suspend period after the second time in which the prefetch operation is disabled.

Abstract: The present application provides a data storage method, a data storage apparatus and a storage system, wherein the method includes: determining a data type of to-be-stored data when the to-be-stored data is obtained (S410); determining a target storage area with a data type same as that of the to-be-stored data based on the data type of data stored in each storage area in the SMR disk (S420); determining in the target storage area a target storage block into which the to-be-stored data is to be written (S430); generating the main index information and backup index information of the to-be-stored data based on the identifier of the target storage block (S440); generating the database index information of the to-be-stored data based on the to-be-stored data and the identifier of the target storage block (S450); and writing the to-be-stored data and the backup index information of the to-be-stored data into the target storage block, writing the main index information of the to-be-stored data into the CMR area or

Abstract: Disclosed herein are system, method, and computer program product embodiments for utilizing an extended cache to access an object store efficiently. An embodiment operates by executing a database transaction, thereby causing pages to be written from a buffer cache to an extended cache and to an object store. The embodiment determines a transaction type of the database transaction. The transaction type can a read-only transaction or an update transaction. The embodiment determines a phase of the database transaction based on the determined transaction type. The phase can be an execution phase or a commit phase. The embodiment then applies a caching policy to the extended cache for the evicted pages based on the determined transaction type of the database transaction and the determined phase of the database transaction.

Abstract: A memory controller that is formed to be able to issue a first write command for writing data of a predetermined length into a DRAM and a second write command for writing data which is less than the predetermined length in the DRAM is provided. The memory controller comprises a deciding unit configured to decide an issuance order of a request stored in the storage unit. In a period from the issuance of a preceding DRAM command until a second write command targeting the same bank as the preceding DRAM command is issued, if another DRAM command targeting a bank different from the bank targeted by the preceding DRAM command can be issued, the deciding unit will decide the issuance order so that the other DRAM command that can be issued will be issued before the second write command.

Abstract: Provided is a data processing system which includes a processor and a storage device, and inputs/outputs data using a learned compander that compresses and expands data, wherein the data processing system comprises an estimation unit which uses learning data and estimates a region of interest to a data model, and a learning unit which causes the compander to learn according to an evaluation function in which each region was weighted based on the region of interest, and a result of the compander compressing and expanding the learning data.

Abstract: A configuration, in which access processing such as data recording from an external device to the archive device can be efficiently performed, is implemented. A data processing section that performs a data recording processing control on a library, which is a data storage section of the archive device is provided. The data processing section saves record data in the local cache section in response to an input of the data recording request from the external device to the library, and outputs a recording processing completion notification to the external device. Further, an elapsed time after the saving in the local cache section is measured, and after the saving in the local cache section, the record data is transferred from the local cache section to the library and recorded after a pre-specified postponement time elapses.

Abstract: Circuitry comprises processing circuitry to access a hierarchy of at least two levels of cache memory storage; memory circuitry comprising plural storage elements, at least some of the storage elements being selectively operable as cache memory storage in respective different cache functions; and control circuitry to allocate storage elements of the memory circuitry for operation according to a given cache function.

Abstract: In various examples, a VPU and associated components may be optimized to improve VPU performance and throughput. For example, the VPU may include a min/max collector, automatic store predication functionality, a SIMD data path organization that allows for inter-lane sharing, a transposed load/store with stride parameter functionality, a load with permute and zero insertion functionality, hardware, logic, and memory layout functionality to allow for two point and two by two point lookups, and per memory bank load caching capabilities. In addition, decoupled accelerators may be used to offload VPU processing tasks to increase throughput and performance, and a hardware sequencer may be included in a DMA system to reduce programming complexity of the VPU and the DMA system. The DMA and VPU may execute a VPU configuration mode that allows the VPU and DMA to operate without a processing controller for performing dynamic region based data movement operations.

Abstract: A memory device includes several normal memory circuits and a redundant memory circuit is disclosed. The several normal memory circuits include several normal memory arrays. The redundant memory circuit includes a redundant memory array. The several normal memory arrays share the redundant memory array. When a first normal memory cell of a first normal memory array of the several normal memory arrays is destructed, a first redundant memory cell of the redundant memory array replaces the first normal memory cell. When a second normal memory cell of a second normal memory array of the several normal memory arrays is destructed, a second redundant memory cell of the redundant memory array replaces the second normal memory cell.

Abstract: Method and apparatus for managing data in a storage device, such as a solid-state drive (SSD). In some embodiments, a data storage device includes a main non-volatile memory (NVM), a host command queue that lists pending host read and host write commands, and a write cache which temporarily stores write data sets pending transfer to the NVM responsive to execution of the associated host write commands in the host command queue. A collision prediction circuit predicts a rate of future collisions involving the cached write data sets. A storage manager directs storage of the write data sets to a first target location responsive to the rate of future collisions being at a first level, and directs storage of the write data sets to a different, second target location responsive to the rate of future collisions being at a different, second level.

Abstract: Embodiments described herein are generally directed to caching and data access improvements in a large scale data processing environment. According to an example, an agent running on a first worker node of a cluster receives a read request from a task. The worker node of the cluster to which the data at issue is mapped is identified. When the first worker node is the identified worker node, it is determined whether its cache contains the data; if so, the data is fetched from a remote data lake and the agent locally caches the data; otherwise, when the identified worker node is another worker node of the compute cluster, the data is fetched from a remote agent of that worker node. The agent responds to the read request with cached data, data returned by the remote data lake, or data returned by the remote data agent as the case may be.

Abstract: A memory system having a stack memory, a set of media. and a controller. The controller divides the stack memory into a plurality of stacks, measures usages of the stacks in a period of time of operating on the set of media, and adjusts partitioning of the stack memory into the plurality of stacks according to the measured usages.

Abstract: A framework disclosed herein extends a relaxed, scoped memory model to a system that includes nodes across a commodity network and maintains coherency across the system. A new scope, cluster scope, is defined, that allows for memory accesses at scopes less than cluster scope to operate on locally cached versions of remote data from across the commodity network without having to issue expensive network operations. Cluster scope operations generate network commands that are used to synchronize memory across the commodity network.

Abstract: An electronic device includes a cache memory and a controller. The cache memory includes a set of cache blocks, each cache block having a number of locations usable for storing cache lines. The cache memory also includes a separate set of error correction code (ECC) bits for each of the locations. The controller stores a victim cache line, evicted from a first location in the cache block, in a second location in the cache block. The controller next stores victim reference information in a portion of the plurality of ECC bits for the first location, the victim reference information indicating that the victim cache line is stored in the second location.

Abstract: A method and system for performing incremental backup of a network attached storage (NAS) device are described. A storage capture instance associated with a first time instance is received from a network attached storage device. At least a portion of metadata of tracked network packets associated with the network attached storage device is also received. At least one changed content item of the network attached storage device that has changed since the first time instance is identified by analyzing the at least the portion of the metadata of the tracked network packets received. An incremental backup of the network attached storage device is performed at a second time instance based at least in part on the at least one changed content item identified.

Abstract: Disclosed herein is an extensible memory subsystem comprising a dual in-line memory module (DIMM) that includes a dynamic random-access memory (DRAM) having a basic memory space, a DIMM memory controller coupled to the DRAM, a memory interface configured to couple the DIMM to a DIMM connector of a computing device, and a first extension interface configured to couple the DIMM to a first remote memory module having a first remote memory space, wherein the DIMM memory controller is configured to map a DIMM memory space comprising the basic memory space of the DRAM and the first remote memory space of the first remote memory module, the DIMM memory space being accessible by the computing device upon the DIMM being coupled to the computing device via the memory interface, and a first remote memory module coupled to the DIMM via the first extension interface of the DIMM.

Abstract: Initialization is performed based on the commands received at the command queue. To perform initialization, a bank touch count list that includes a list of banks being accessed by the commands and a bank touch count for each of the banks in the list is updated. The bank touch count identifies the number of commands accessing each of the banks. The bank touch count list is updated by assigning a bank priority rank to each of the banks based on their bank touch count, respectively. Once initialized, the commands in the command queue are scheduled by inserting each of the commands into priority queues based on the bank touch count list.

Abstract: Exemplary methods, apparatuses, and systems include identifying that a first cache line from a first cache is subject to an operation that copies data from the first cache to a non-volatile memory. A first portion of the first cache line stores clean data and a second portion of the first cache line stores dirty data. A redundant copy of the dirty data is stored in a second cache line of the first cache. In response to identifying that the first cache line is subject to the operation, metadata associated with the redundant copy of the dirty data is used to copy the dirty data to a non-volatile memory while omitting the clean data.

Abstract: A request node is provided comprising request circuitry to issue write requests to write data to storage circuitry. The write requests are issued to the storage circuitry via a coherency node. Status receiving circuitry receives a write status regarding write operations at the storage circuitry from the coherency node and throttle circuitry throttles a rate at which the write requests are issued to the storage circuitry in dependence on the write status. A coherency node is also provided, comprising access circuitry to receive a write request from a request node to write data to storage circuitry and to access the storage circuitry to write the data to the storage circuitry. Receive circuitry receives, from the storage circuitry, an incoming write status regarding write operations at the storage circuitry and transmit circuitry transmits an outgoing write status to the request node based on the incoming write status.

Abstract: A method, a computing device, and a non-transitory machine-readable medium for modifying cache settings in the array cache are provided. Cache settings are set in an array cache, such that the array cache caches data in an input/output (I/O) stream based on the cache settings. Multiple cache simulators simulate the caching the data from the I/O stream in the array cache using different cache settings in parallel with the array cache. The cache settings in the array cache are replaced with the cache settings from one of the cache simulators based on the determination that the cache simulators increase effectiveness of caching data in the array cache.