Abstract: Embodiments of a system for dynamic reconfiguration of cache are disclosed. Accordingly, the system includes a plurality of processors and a plurality of memory modules executed by the plurality of processors. The system also includes a dynamic reconfigurable cache comprising of a multi-level cache implementing a combination of an L1 cache, an L2 cache, and an L3 cache. The one or more of the L1 cache, the L2 cache, and the L3 cache are dynamically reconfigurable to one or more sizes based at least in part on an application data size associated with an application being executed by the plurality of processors. In an embodiment, the system includes a reconfiguration control and distribution module configured to perform dynamic reconfiguration of the dynamic reconfigurable cache based on the application data size.

Abstract: A technique for transferring data in a digital signal processing system is described. In one example, the digital signal processing system comprises a number of fixed function accelerators, each connected to a memory access controller and each configured to read data from a memory device, perform one or more operations on the data, and write data to the memory device. To avoid hardwiring the fixed function accelerators together, and to provide a configurable digital signal processing system, a multi-threaded processor controls the transfer of data between the fixed function accelerators and the memory. Each processor thread is allocated to a memory access channel, and the threads are configured to detect an occurrence of an event and, responsive to this, control the memory access controller to enable a selected fixed function accelerator to read data from or write data to the memory device via its memory access channel.

Abstract: Methods for determining cache activity and for optimizing cache reclamation are performed by systems and devices. A cache entry access is determined at an access time, and a data object of the cache entry for a current time window is identified that includes a time stamp for a previous access and a counter index. A conditional counter operation is then performed on the counter associated with the index to increment the counter when the time stamp is outside the time window or to maintain the counter when the time stamp is within the time window. A counter index that identifies another counter for a previous time window where the other counter value was incremented for the previous cache entry access causes the other counter to be decremented. A cache configuration command to reclaim, or additionally allocate space to, the cache is generated based on the values of the counters.

Abstract: The storage device includes a first memory, a process device that stores data in the first memory and reads the data from the first memory, and an accelerator that includes a second memory different from the first memory. The accelerator stores compressed data stored in one or more storage drives storing data, in the second memory, decompresses the compressed data stored in the second memory to generate plaintext data, extracts data designated in the process device from the plaintext data, and transmits the extracted designated data to the first memory.

Abstract: Aspects of the present disclosure provide a computer-implemented method that includes providing a layered index to variable length data, the layered index comprising a plurality of layers. Each layer of the plurality of layers has an index array, a block offset array, and a per-block size array. The index array identifies a next level index of a plurality of indices or data. The indices represent a delta value from a first index of a block. The block offset array identifies a starting location of the index array. The per-block array identifies a shared integer size of a block of indices. The method further includes performing a random access read of the variable length data using the layered index.

Abstract: Apparatus comprises source circuitry to provide data items; buffer circuitry having a set of buffer entries to hold one or more data items, provided by the source circuitry, for delivery to one or more destinations within a respective delivery latency, in which a buffer entry holding an initial data item becomes available to hold another data item in response to delivery of the initial data item to its respective destination; and control circuitry to control acceptance of data items from the source circuitry for holding by the buffer circuitry, the control circuitry being configured to control the buffer circuitry to accept a given data item when: (i) a buffer entry is available to hold the given data item and (ii) the delivery latency of data items including the given data item held by the buffer circuitry is such that at least a threshold number of buffer entries may be made available within no more than a threshold availability period.

Abstract: A system for data migration is disclosed. The system may receive a migration request comprising a source file path and a target file location. The system may capture source file metadata based on the source file path and the migration request. The system may transfer a source file from a first data environment to an intermediate data environment via a first transfer process. The system may transfer the source file from the intermediate data environment to a second data environment via a second transfer process.

Abstract: Methods and systems for backing up and restoring sets of electronic files using sets of pseudo-virtual disks are described. The sets of electronic files may be sourced from or be stored using one or more different data sources including one or more real machines and/or one or more virtual machines. A first snapshot of the sets of electronic files may be aggregated from the different data sources and stored using a first pseudo-virtual disk. A second snapshot of the sets of electronic files may be aggregated from the different data sources subsequent to the generation of the first pseudo-virtual disk and stored using the first pseudo-virtual disk or a second pseudo-virtual disk different from the first pseudo-virtual disk.

Abstract: Techniques are disclosed for processing address translations. The techniques include detecting a first miss for a first address translation request for a first address translation in a first translation lookaside buffer, in response to the first miss, fetching the first address translation into the first translation lookaside buffer and evicting a second address translation from the translation lookaside buffer into an instruction cache or local data share memory, detecting a second miss for a second address translation request referencing the second address translation, in the first translation lookaside buffer, and in response to the second miss, fetching the second address translation from the instruction cache or the local data share memory.

Abstract: Example distributed storage systems, controller nodes, and methods provide distributed and redundant data blocks accessed based on storage path cost values. Storage elements are accessible through hierarchical storage paths traversing multiple system components. Data blocks are distributed among the storage elements. System costs are calculated based on the storage path for reaching each storage element and a storage path is selected based on a comparison of the system costs for each storage element. Data blocks are accessed through the selected storage path.

Abstract: Exemplary methods, apparatuses, and systems include identifying that a first cache line from a first cache is subject to an operation that copies data from the first cache to a non-volatile memory. A first portion of the first cache line stores clean data and a second portion of the first cache line stores dirty data. A redundant copy of the dirty data is stored in a second cache line of the first cache. In response to identifying that the first cache line is subject to the operation, metadata associated with the redundant copy of the dirty data is used to copy the dirty data to a non-volatile memory while omitting the clean data.

Abstract: A method configures a cache to implement a LRU management technique. The cache has N entries divided into B buckets. Each bucket has a number of entries equal to P entries*M vectors, wherein N=B*P*M. Any P entry within any M vector is ordered using an in-vector LRU ordering process. Any entry within any bucket is ordered in LRU within the vectors and buckets. The LRU management technique moves a found entry to a first position within a same M vector, responsive to a lookup for a specified key, and permutes the found entry and a last entry in a previous M vector, responsive to the found entry already being in the first position within a vector and the same one of the M vectors not being a first vector in the bucket in the moving step.

Abstract: A method for managing a cache memory of a storage system, the method may include receiving, by a controller of the storage system, an access request related to a data unit; wherein the receiving occurs while (a) the cache memory stores a group of oldest cached data units, and (b) the data unit is stored in a memory module of the storage system the differs from the cache memory; determining, by the controller, a caching category of the data unit; and preventing from caching the data unit in the cache memory when a hit score of the caching category of the data unit is lower than a hit score of the group of oldest cached data units; and caching the data unit in the cache memory when the hit score of the caching category of the data unit is higher than the hit score of the group of oldest cached data units; wherein the hit score of the caching category of the data unit is indicative of a probability of a cache hit per data unit of the caching category.

Abstract: A storage system comprises a disk array enclosure comprising an enclosure controller, a cache comprising a metadata journal, a plurality of data storage devices and a plurality of metadata storage devices. The enclosure controller is configured to write a stripe metadata page to the metadata storage devices that corresponds to a stripe of data stored on the data storage devices and to determine that the write of the stripe metadata page failed for a first metadata storage device. The enclosure controller is configured to add an entry to the metadata journal based on the determination that the write failed. The entry comprises an indication of the first metadata storage device and the stripe of data. The enclosure controller is configured to set an indication in a data structure associated with the disk array enclosure that the stripe metadata page has not been written to the first metadata storage device.

Abstract: A processor of an aspect includes an instruction pipeline to process a multiple memory address instruction that indicates multiple memory addresses. The processor also includes multiple page fault aggregation logic coupled with the instruction pipeline. The multiple page fault aggregation logic is to aggregate page fault information for multiple page faults that are each associated with one of the multiple memory addresses of the instruction. The multiple page fault aggregation logic is to provide the aggregated page fault information to a page fault communication interface. Other processors, apparatus, methods, and systems are also disclosed.

Abstract: A memory device to perform a calibration of read voltages of a group of memory cells. For example, the memory device can measure signal and noise characteristics of a group of memory cells to determine an optimized read voltage of the group of memory cells and determine an amount of accumulated storage charge loss in the group of memory cells. Subsequently, the memory device can perform a read voltage calibration based on the determined amount of accumulated storage charge loss and a look up table.

Abstract: A processing system includes a cache, a host memory, a CPU and a hardware accelerator. The CPU accesses the cache and the host memory and generates at least one instruction. The hardware accelerator operates in a non-temporal access mode or a temporal access mode according to the access behavior of the instruction. The hardware accelerator accesses the host memory through an accelerator interface when the hardware accelerator operates in the non-temporal access mode, and accesses the cache through the accelerator interface when the hardware accelerator operates in the temporal access mode.

Abstract: A predictive storage management system includes a storage system having storage devices, and a predictive storage management device coupled to the storage system via a network. The predictive storage management device includes a statistical time-series storage device usage sub-engine that retrieves first storage device usage data from a first storage device in the storage system and uses it to generate a first storage device usage trend model. A machine-learning storage system usage sub-engine in the predictive storage management device retrieves storage system implementation information from the storage system and uses it to generate a storage system implementation model. A storage management sub-engine in the predictive storage management device analyzes the first storage device usage trend model and the storage system implementation model to predict future usage of the first storage device and, based on that predicted future usage, performs a management action associated with the first storage device.

Abstract: A plurality of pieces of write data are aggregated on a buffer to obtain a segment where the segment exceeds a smallest write size supported by storage. An address on the storage is determined for the segment. Location information and identifier(s) associated with the segment are recorded where the location information points to the storage, as opposed to the buffer, while the write data is being aggregated. When the write data has been aggregated into the segment, the segment is written to the storage wherein the location information remains unchanged in response to the writing to the storage.

Abstract: To perform Recovery Point Objective (RPO) driven backup scheduling, the illustrative data storage management system is enhanced in several dimensions. Illustrative enhancements include: streamlining the user interface to take in fewer parameters; backup job scheduling is largely automated based on several factors, and includes automatic backup level conversion for legacy systems; backup job priorities are dynamically adjusted to re-submit failed data objects with an “aggressive” schedule in time to meet the RPO; only failed items are resubmitted for failed backup jobs.