Abstract: Described methods and systems for copying a source volume to a target volume that include a combination of concurrent copying and a copy-on-write (COW) technique that improves the reliability of the backup process and requires fewer resources during a given backup instance than the processes of the prior art.

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. In various embodiments, a computing system includes one or more computing resources and a memory controller coupled to a memory device. The memory controller determines a memory access request targets a given bank of multiple banks. An access history is updated for the given bank based on whether the memory access request hits on an open page within the given bank and a page hit rate for the given bank is determined. The memory controller sets an idle cycle limit based on the page hit rate. The idle cycle limit is a maximum amount of time the given bank will be held open before closing the given bank while the bank is idle. The idle cycle limit is based at least in part on a page hit rate for the bank.

Abstract: A method and system for assessing sequentiality of a data stream is disclosed. Specifically, the method and system disclosed herein may entail receiving an incoming request to access a page in a cache memory, wherein the page is identified by a page address of an address space in a main memory; identifying, in a memory, a bin corresponding to an address range including the page address of the page of the incoming request, wherein the bin includes k address ranges of the address space of the main memory; determining whether to update an occupation count of the bin in the memory; locating the bin in a heuristics table to obtain an estimated total number of expected proximal accesses based on an updated occupation count of the bin; and determining, based on the estimated total number of expected proximal accesses, sequentiality of the data stream to device in order to generate a policy for the cache memory.

Abstract: The described technology is generally directed towards fault tolerant cluster data handling techniques, as well as devices and computer readable media configured to perform the disclosed fault tolerant cluster data handling techniques. Nodes in a computing cluster can be configured to generate wire format resources corresponding to operating system resources. A wire format resource can comprise a cache key and a hint information to locate data, such as a file, corresponding to the operating system resource. The wire format resource can be stored in a resource cache along with a pointer that points to the operating system resource. The wire format resource can also be provided to client devices. Nodes in the computing cluster can be configured to receive and process client instructions that include wire format resources, as well as to use hint information to re-allocate data associated with a wire format resource.

Abstract: According to one embodiment, a memory system includes a nonvolatile memory including a plurality of memory chips and a controller. The controller acquires a first command from a first queue, transmits the acquired first command to a first memory chip, thereafter acquires a second command from a second queue, and transmit the acquired second command to a second memory chip when a first command processing speed based on a time until execution of a command using the first memory chip is completed after transmission of the command to the first memory chip is started is lower than a second command processing speed based on a time until execution of a command using the second memory chip is completed after transmission of the command to the second memory chip is started.

Abstract: Embodiments are provided for reducing data using a plurality of compression operations in a computing storage environment. A speed of data writing to a virtual tape device and an availability of one or more processor devices for the virtual tape device may be monitored. One or more requests may be received for writing data to the virtual tape device. Data to be written to the virtual tape device, corresponding to a selected number of the one or more requests for writing the data, may be compressed according to both the speed of data writing to the virtual tape device and the availability of one or more processor devices for the virtual tape device. The compressed data may be stored in the virtual tape device in record units. Non-compressed data may be compressed in the virtual tape device at a subsequent period of time (e.g., future time period).

Abstract: A cache subsystem is disclosed. The cache subsystem includes a cache configured to store information in cache lines arranged in a plurality of ways. A requestor circuit generates a request to access a particular cache line in the cache. A prediction circuit is configured to generate a prediction of which of the ways includes the particular cache line. A comparison circuit verifies the prediction by comparing a particular address tag associated with the particular cache line to a cache tag corresponding to a predicted one of the ways. Responsive to determining that the prediction was correct, a confirmation indication is stored indicating the correct prediction. For a subsequent request for the particular cache line, the cache is configured to forego a verification of the prediction that the particular cache line is included in the one of the ways based on the confirmation indication.

Abstract: Methods, apparatus, and processor-readable storage media for tracking data mirror differences are provided herein. An example computer-implemented method includes obtaining a request to start tracking data differences between a plurality of data mirror volumes of a storage system, wherein the storage system is configured to apply at least a first data tracking technique that tracks the data differences using one or more bitmap records and a second data tracking technique that tracks the data differences using or more journal records; selecting at least one of the first data tracking technique and the second data tracking technique using one or more selection criteria; and tracking the data differences in accordance with the selected at least one data tracking technique.

Abstract: Managing pool memory in a data storage system includes maintaining free lists for corresponding object sizes. For a memory-consuming request (e.g., host write) an allocation operation is performed and the request data is stored. The allocation operation includes (1) selecting a memory object at least as large as the request size and removing all pages of the selected memory object from the corresponding free list, and (2) selecting pages of the selected memory object to store the request data and marking the selected pages as non-free, and leaving any leftover pages as free pages. For a memory-freeing request (e.g., destaging), a deallocation operation is performed that includes (1) marking the request pages free, and (2) based on neighboring pages being free, merging the request pages and neighboring pages into a corresponding memory object and adding the merged pages to the corresponding free list.

Abstract: A storage device set is provided. The storage device set includes a reconfigurable logic chip and a storage device. The logic chip includes a retimer configured to generate an output signal by adjusting an input signal received from an external device; and an operation circuit configured to perform an operation function. The storage device includes: a first port connected to the retimer; a second port connected to the operation circuit; and a controller configured to control data transmission and reception via the first port and the second port.

Abstract: A target-less point in time image (snapshot) of a storage volume is allowed to be built after activation, by enabling the snapshot data to be modified to create a crash-consistent replica of the source data after the snapshot has been activated. The data of the snapshot remains immutable from a user standpoint, but the snapshot is able to be quickly activated before all of the data of the snapshot has been included in the snapshot, to thus reduce an amount of time IO operations on the source volume are quiesced. A first snapshot of a storage volume is created on a primary storage system and a corresponding second snapshot of the storage volume is activated on a backup storage system before all the data of the first snapshot is received at the backup storage system. Entries of the activated second snapshot are then changed to point to correct back-end allocations.

Abstract: Technologies for logging and visualizing trace capture data in a data storage subsystem (e.g., storage application layers and data storage devices of a compute device) are disclosed herein. One or more storage events in the data storage subsystem are captured for a specified time period. Statistics are determined from the captured storage events. A visualization of the storage events and statistics for the specified time period is generated.

Abstract: Access control is achieved in consideration of write training. Masters issue access requests including a read request and a write request. A memory controller accesses memory in response to the access requests issued by the maters. A central bus-control system controls the output of the access requests issued by the masters to the memory controller. A training circuit conducts training on the memory while the access to the memory is stopped. The central bus-control system further controls the execution of the training on the memory. During the training, the central bus-control system suppresses the output of the read request to the memory controller from among the access requests issued by the masters.

Abstract: Embodiments are directed to managing data in a file system. A file system that includes a file storage tier and a cache storage tier may be provided. An amount of hot blocks present in the cache storage tier that are associated with a heat score that matches a maximum heat score value may be determined. In response to the amount of hot blocks exceeding an amount threshold value further actions may be performed, including: determining each cooldown block in the cache storage tier based on each heat score associated with each block in the cache storage tier; and decrementing the heat score associated with each cooldown block. In response to one or more blocks in the cache storage tier being read, the heat score associated with the one or more blocks being read may be set to the maximum heat score value.

Abstract: A method and apparatus for caching a data block are provided. The method includes: obtaining, from a terminal, an access request for requesting access to a first data block; determining that the first data block is missed in a cache space of a storage system; detect whether a second data block satisfies a lazy condition, the second data block being a candidate elimination block in the cache space and the lazy condition being a condition for determining whether to delay replacing the second data block from the cache space according to a re-access probability; determining that the second data block satisfies the lazy condition; and accessing the first data block from a storage space of the storage system and skipping replacing the second data block from the cache space.

Abstract: Provided is a storage system in which a compression rate of randomly written data can be increased and access performance can be improved. A storage controller 22A includes a cache area 203A configured to store data to be read out of or written into a drive 29. The controller 22A groups a plurality of pieces of data stored in the cache area 203A and input into the drive 29 based on a similarity degree among the pieces of data, selects a group, compresses data of the selected group in group units, and stores the compressed data in the drive 29.

Abstract: A method comprises configuring an address-to-SC unit (A2SU) of each of a plurality of CPU chips based on a number of valid SC chips in the computer system. Each of the plurality of CPU chips is coupled to each of the SC chips in a leaf-spine topology. The A2SU is configured to correlate each of a plurality of memory addresses with a respective one of the valid SC chips. The method further comprises, in response to detecting a change in the number of valid SC chips, pausing operation of the computer system including operation of a cache of each of the plurality of CPU chips; while operation of the computer system is paused, reconfiguring the A2SU in each of the plurality of CPU chips based on the change in the number of valid SC chips; and in response to reconfiguring the A2SU, resuming operation of the computer system.

Abstract: Periodic signal timing calibration is implemented in time-distributed fragments executed concurrently with occasional system-idling maintenance operations to maintain reliable synchronous communication between interconnected system components without impacting system availability.

Abstract: Certain embodiments described herein relate to an improved disk usage growth prediction system. In some embodiments, one or more components in an information management system can determine usage status data of a given storage device, perform a validation check on the usage status data using multiple prediction models, compare validation results of the multiple prediction models to identify the best performing prediction model, generate a disk usage growth prediction using the identified prediction model, and adjust the available space of the storage device according to the disk usage growth prediction.

Abstract: A memory controller that includes, in one implementation, a memory interface and a controller circuit. The memory interface is configured to interface with a non-volatile memory. The controller circuit is configured to receive a skewed codeword read from the non-volatile memory. The controller circuit is also configured to scan the skewed codeword by inserting or removing a quantity of bits at different locations in the skewed codeword and determining resulting syndrome weights of the skewed codeword. The controller circuit is further configured to determine an adjusted codeword by inserting or removing the quantity of bits at one of the different locations in the skewed codeword which results in a smallest syndrome weight. The controller circuit is also configured to decode the adjusted codeword.