Abstract: A system and method relates to detecting a hardware event, determining a first virtual memory address associated with the hardware event, wherein the first virtual memory address is associated with a first processing thread, identifying, using the first virtual memory address, an entry of a logical address table, the entry comprising a file descriptor and a file offset associated with a file, identifying a memory address table associated with the file descriptor, translating, using the memory address table, the file offset into a second virtual memory address associated with a second processing thread, and transmitting, to the second processing thread, a notification comprising the second virtual memory address.

Abstract: An approach is disclosed that relocates a named data element. A request to move a name corresponding to the named data element is received from a first storage area in a Coordination Namespace to a second storage area in the Coordination Namespace. The first storage area has a first level of persistence, and the second storage area has a second level of persistence. The named data element exists in a Coordination Namespace that is allocated in a memory distributed amongst a plurality of nodes that include the local node and one or more remote nodes. The approach then creates a copy of the named data element in the second storage area.

Abstract: Initialization is performed based on the commands received at the command queue. To perform initialization, a bank touch count list that includes a list of banks being accessed by the commands and a bank touch count for each of the banks in the list is updated. The bank touch count identifies the number of commands accessing each of the banks. The bank touch count list is updated by assigning a bank priority rank to each of the banks based on their bank touch count, respectively. Once initialized, the commands in the command queue are scheduled by inserting each of the commands into priority queues based on the bank touch count list.

Abstract: According to an embodiment, a storage controller includes a collector and a controller. The collector is configured to collect data to be written in nonvolatile storage. The controller is configured to perform controlling such that a first time length between collecting data and writing the collected data in the nonvolatile storage after an emergency prediction notice is received is shorter than a second time length between collecting data and writing the collected data in the nonvolatile storage before the emergency prediction notice is received.

Abstract: A computer-implemented method according to one embodiment includes receiving, from an application at a metadata node of a clustered computing system, a request for a file, identifying, by the metadata node, a subset of data nodes within the clustered computing system where a portion of the file is stored, determining, by the metadata node, a data node within the subset of data nodes storing the portion of the file in a cache of the data node, and returning to the application, by the metadata node, a location of the portion of the file at the data node storing the portion of the file in the cache of the data node.

Abstract: Some examples described herein provide for a partially coherent memory transfer. An example method includes moving data directly from a coherence domain of an originating symmetric multiprocessor (SMP) node across a memory fabric to a target location for the data within a coherence domain of a receiving SMP node.

Abstract: According to examples, a system may include a central processing unit (CPU) and a capability enforcement controller in communication with the CPU. The capability enforcement controller may be separate from the CPU and may implement capability processing functions that control capabilities. Capabilities may be defined as unforgeable tokens of authority that protect access by the CPU to a physical address at which the data is stored in a memory.

Abstract: A method for efficiently method for performing adaptive management of a cache with predetermined size and number of cells with different locations with respect to the top or bottom of the cache, for storing at different cells, data items to be retrieved upon request from a processor. A stream of requests for items, each of which has a temporal probability to be requested is received and the jump size is incremented on cache misses and decremented on cache hits by automatically choosing a smaller jump size and using a larger jump size when the probability of items to be requested is changed. The jump size represents the number of cells by which a current request is promoted in the cache, on its way from the bottom, in case of a cache hit, or from the outside in case of a cache miss, towards the top cell of the cache.

Abstract: Disclosed herein are methods, systems, and processes to improve application performance in replication environments. In one embodiment, first application input/output (I/O) throughput and second application I/O throughput are associated with a data volume and are both sampled, with the first application I/O throughput being sampled while the data volume is set to an asynchronous write acknowledgement mode and the second application I/O throughput being sampled while the data volume is set to a synchronous write acknowledgement mode. A determination is made as to whether the asynchronous write acknowledgement mode or the synchronous write acknowledgement mode provides a higher application I/O throughput for the data volume. The data volume is then set to a preferred write acknowledgement mode that is selected, based on a result of the determining, from the asynchronous write acknowledgement mode and the synchronous write acknowledgement mode, and in certain embodiments, a mixed write acknowledgement mode.

Abstract: The Source Volume Backup with Predictive and Lookahead Optimizations Apparatuses, Methods and Systems (“SVBAF”) transforms backup request inputs via SVBAF components into backup response outputs. A set of blocks to be copied from a source volume to a target volume is designated based on predictive optimization settings and copied based on lookahead optimization settings while an operating system is configured to write to the source volume. Blocks of the source volume that were written to by the operating system are identified. A determination is made whether to enter a CoW mode. If the CoW mode should not be entered, the designated set of blocks is changed to include at least one of the identified blocks and a pass is repeated. Otherwise, the operating system is instructed to enter the CoW mode and bring the target volume into a state consistent with a state of the source volume.

Abstract: Scaling events may be detected for hosting hierarchical data structures. Scaling events may be detected to modify the capacity of a data store for hierarchical data structures to handle changing write workloads, read workloads, or storage capacity. Hierarchical data structures may be moved from one group of storage hosts to another group of storage hosts according to a filtered snapshot that includes the hierarchical data structures to be moved that is provided to the destination storage hosts. Changes made to the hierarchical data structures made at the source storage hosts during the move can be applied to the filtered snapshot so that the hierarchical data structures may be made available at the destination storage hosts inclusive of the changes.

Abstract: The present application proposes a memory chip includes a plurality of memory banks, a plurality of address pins, and a pseudo-address determining circuit. The plurality of address pins is arranged for receiving a plurality of address signals corresponding to the plurality of memory banks, respectively. The pseudo-address determining circuit has a plurality of input terminals coupled to the plurality of address pins, respectively, and a plurality of output terminals coupled to the plurality of memory banks. The pseudo-address determining circuit generates a pseudo-address table for the plurality of memory banks when the memory chip is powered-up. The pseudo-address table has a plurality of pseudo-addresses corresponding to the plurality of memory banks, respectively. The present application also provides a memory module that incorporates the memory chip and a method for pseudo-accessing memory banks of the memory chip.

Abstract: According to embodiments described herein, the hierarchical complexity for coherence protocols associated with clustered cache architectures can be encapsulated in a simple function, i.e., that of determining when a data block is shared entirely within a cluster (i.e., a sub-tree of the hierarchy) and is private from the outside. This allows embodiments to eliminate complex recursive coherence operations that span the hierarchy and instead employ simple coherence mechanisms such as self-invalidation and write-through but which are restricted to operate where a data block is shared. Thus embodiments recognize that, in the context of clustered cache hierarchies, data can be shared entirely within one cluster but can be private (unshared) to this cluster when viewed from the perspective of other clusters. This characteristic of the data can be determined and then used to locally simplify coherence protocols.

Abstract: A non-volatile storage apparatus includes a set of non-volatile memory cells and one or more control circuits in communication with the set of non-volatile memory cells. The one or more control circuits are configured to group physical addresses of the set of non-volatile memory cells into groups of configurable sizes and to individually apply wear leveling schemes to non-volatile memory cells of a group.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for hybrid dual write. An apparatus includes a memory device comprising a plurality of single level cell blocks and a plurality of multi level cell blocks. An apparatus includes a hybrid writing component. A hybrid writing component includes a single level writing circuit that writes data to a plurality of single level cell blocks. A hybrid writing component includes a multi level writing circuit that copies data from a plurality of single level cell blocks to a plurality of multi level cell blocks. A hybrid writing component includes a control circuit that controls data to be copied from a single level cell block of a plurality of single level cell blocks to at least two multi level cell blocks of a plurality of multi level cell blocks.

Abstract: Apparatuses, systems, methods, and computer program products are disclosed for hybrid dual write. An apparatus includes a memory device comprising a plurality of single level cell blocks and a plurality of multi level cell blocks. An apparatus includes a hybrid writing component. A hybrid writing component includes a single level writing circuit that writes data to a plurality of single level cell blocks. A hybrid writing component includes a multi level writing circuit that copies data from a plurality of single level cell blocks to a plurality of multi level cell blocks. A hybrid writing component includes an allocation circuit that allocates a single level cell block of a plurality of single level cell blocks to a first stream in response to a multi level cell block of a plurality of multi level cell block being allocated to the first stream.

Abstract: Examples include storage class memory (SCM) queue depth threshold adjustment. Examples may adjust the SCM queue depth threshold of a controller based on whether an IO request latency threshold for an SCM read cache is exceeded. Examples may determine whether to process an IO request using the SCM read cache based on an SCM queue depth of the controller and the SCM queue depth threshold.

Abstract: A first entropy indicator is calculated at a first time for a collection of data stored in at least one memory. A second entropy indicator is calculated at a second time for the collection of data. The first entropy indicator is compared with the second entropy indicator. Based on the comparison, it is determined whether to back up the collection of data and/or whether to retain an earlier backup of the collection of data.

Abstract: Several embodiments of memory devices and systems with removable storage are disclosed herein. In one embodiment, a non-volatile dual in-line memory module (NVDIMM) includes a controller and a non-volatile memory slot configured to operatively connect a removable non-volatile memory device to the controller. The NVDIMM further comprises one or more volatile memories operatively connected to the controller. The controller is configured to backup content on the one or more volatile memories onto a removable non-volatile memory device operatively connected to the controller via the non-volatile memory slot. In some embodiments, the NVDIMM further comprises dedicated hardware configured to direct the controller to backup content on the one or more volatile memories onto a removable non-volatile memory device operatively connected to the controller via the non-volatile memory slot.

Abstract: A memory system includes a memory blade including a plurality of operation memories; and a controller coupled to the memory blade, wherein the controller includes: a data base (DB) memory suitable for storing a data base (DB) having first information, which is an average usage amount of an operation memory used for processing a generated target workload, as a field and workloads as an entry; an allocation unit suitable for allocating an usage amount of an operation memory for processing a current target workload based on a value of the first information stored in the DB, corresponding to the current target workload requested to be processed; and a monitor suitable for updating the value of the first information to the average usage amount of the operation memory allocated for processing the current target workload after the processing of the current target workload is completed.