Patents Examined by William E Baughman
  • Patent number: 11237923
    Abstract: A method and system for performing incremental backup of a network attached storage (NAS) device are described. A storage capture instance associated with a first time instance is received from a network attached storage device. At least a portion of metadata of tracked network packets associated with the network attached storage device is also received. At least one changed content item of the network attached storage device that has changed since the first time instance is identified by analyzing the at least the portion of the metadata of the tracked network packets received. An incremental backup of the network attached storage device is performed at a second time instance based at least in part on the at least one changed content item identified.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: February 1, 2022
    Assignee: Cohesity, Inc.
    Inventors: Prashant Pogde, Sunil Moolchandani, Mohit Aron, Markose Thomas
  • Patent number: 11231867
    Abstract: Techniques for processing write operations may include: receiving, at a first data storage system, a first write operation that writes first data to a first device, wherein the first device is configured for replication on a second device of a second data storage system; performing first processing that determines whether the first data written by the first write operation is a duplicate of an existing entry in a first hash table of the first data storage system; responsive to determining the first data written by the first write operation is a duplicate of an existing entry in the first hash table, performing second processing; responsive to determining the first data written by the first write operation is unique and is not a duplicate of an existing entry in the first hash table, performing third processing; and transmitting the final buffer to the second data storage system.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: January 25, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Venkata L R Ippatapu, Kenneth Dorman
  • Patent number: 11233874
    Abstract: A method for performing a write operation in a distributed storage system is disclosed. The method comprises receiving a first time-stamped write request from a proxy server. Further, the method comprises determining if the first time-stamped write request is within a time window of a reorder buffer and if the first time-stamped write request overlaps with a second time-stamped write request in the reorder buffer. Responsive to a determination that the first time-stamped write request is outside the time window or that the first time-stamped write request is within the time window but has an older time-stamp than the second time-stamped write request, the method comprises rejecting the first time-stamped write request. Otherwise, the method comprises inserting the first time-stamped write request in the reorder buffer in timestamp order and transmitting an accept to the proxy server.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: January 25, 2022
    Assignee: VMware, Inc.
    Inventor: Guillermo J. Rozas
  • Patent number: 11232031
    Abstract: A memory allocation method and a device, where the method is applied to a computer system including a processor and a memory, and comprises, after receiving a memory access request carrying a to-be-accessed virtual address and determining that no memory page has been allocated to the virtual address, the processor selecting a target rank group from at least two rank groups of the memory based on access traffic of the rank groups. The processor selects, from idle memory pages, a to-be-allocated memory page for the virtual address, where information about a first preset location in a physical address of the to-be-allocated memory page is the same as first portions of address information in addresses of ranks in the target rank group.
    Type: Grant
    Filed: May 22, 2019
    Date of Patent: January 25, 2022
    Assignee: Huawei Technologies Co., Ltd.
    Inventors: Shihai Xiao, Xing Hu, Kanwen Wang, Wei Yang
  • Patent number: 11231876
    Abstract: An example system may provide for plurality of object block stores and a store management system. The store management system is configured to access a first bucket including a first storage class bucket tag identified by a first key-value pair corresponding to a first one of the plurality of object block stores with a first storage class. The store management system is further configured to write a first data object to the first one of the plurality of object block stores with a first storage class. The first one of the plurality of object block stores is represented by the first bucket. The first one of the plurality of object block stores is configured to store the first data object according to the first storage class specified by the first storage class bucket tag.
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: January 25, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventor: Sudhish Panamthanath Thankappan
  • Patent number: 11221793
    Abstract: Embodiments of three-dimensional (3D) memory devices with a 3D NAND memory array having a plurality of pages and an on-die data buffer coupled to the memory array on a same chip and configured to buffer a plurality of batches of program data between a host and the memory array. The on-die data buffer may include SRAM cells. The 3D memory device also includes a controller coupled to the on-die data buffer on the same chip. The controller may be configured to receive control instructions for performing a first pass program and a second pass program on memory cells in a page. The controller may also be configured to buffer, in the on-die data buffer, first program data for a first pass program and second program data for a second pass program from a host and retrieve the first program data from the on-die data buffer.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: January 11, 2022
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventors: Yue Ping Li, Wei Jun Wan, Chun Yuan Hou
  • Patent number: 11210032
    Abstract: The present invention realizes a storage device that has a high data reduction effect without decreasing I/O performances. The storage device includes a processor, an accelerator, a memory, and a storage medium, the processor specifies data to be compressed that is data stored in the storage medium from data stored in the memory and transmits a compression instruction including information relating to the data to be compressed to the accelerator, and the accelerator reads the plurality of continuous items of data from the memory and compresses the plurality of items of data to be compressed obtained by excluding data that is not to be compressed from the plurality of items of data, based on the information relating to the data to be compressed received from the processor, to generate compressed data stored in the storage device.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: December 28, 2021
    Assignee: HITACHI, LTD.
    Inventors: Takashi Nagao, Tomohiro Yoshihara, Akira Yamamoto, Yuusaku Kiyota
  • Patent number: 11210209
    Abstract: The present invention provides a method for managing a flash memory module, wherein the flash memory module includes a plurality of flash memory chips, each flash memory chip includes a plurality of blocks, and each block includes a plurality of pages, and the method includes the steps of: using a time management circuit to generate current time information; when data is written into any one of the blocks, recording the time information generated by the time management circuit; and determining at least one specific block according to quantity of invalid pages within each block and the time information of each block.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: December 28, 2021
    Assignee: Silicon Motion, Inc.
    Inventors: Jian-Dong Du, Pi-Ju Tsai, Tsung-Chieh Yang
  • Patent number: 11194722
    Abstract: Apparatus and method for improved cache utilization and efficiency on a many-core processor. An apparatus comprising: a plurality of execution units to generate cache access requests responsive to executing instructions; a pending request queue to store pending cache access requests generated by the execution units; pending queue management circuitry to compare a current cache access request with entries in the pending request queue to determine whether the current cache access request can be merged with an entry in the pending request queue and, if so, to merge the current cache access request with the entry.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: December 7, 2021
    Assignee: INTEL CORPORATION
    Inventors: Bharath Narasimha Swamy, Joydeep Ray, Rama Kishan Malladi, James Valerio, Abhishek Appu
  • Patent number: 11188232
    Abstract: Techniques for evaluating data sets for compression processing may include: receiving first information for a data set, the first information including I/O activity information for the data set, a service level objective for the data set, and a size of the data set; determining, in accordance with the first information, whether the data set meets criteria indicating a specified level of importance and a specified level of I/O activity; responsive to determining the data set meets the criteria, sending second information identifying one or more storage objects of the data set to a compression engine, wherein the one or more storage objects of the data set are identified as having the specified level of importance and at least the specified level of I/O activity; and performing processing, by the compression engine using the second information, to determine whether to compress first data stored in the data set.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: November 30, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Paul J. McSweeney, Ciara Stacke, Andrea Graham
  • Patent number: 11182307
    Abstract: A method for demoting data elements from a cache is disclosed. The method maintains a heterogeneous cache comprising a higher performance portion and a lower performance portion. The method maintains, within the lower performance portion, a ghost cache containing statistics for data elements that are currently contained in the heterogeneous cache, and data elements that have been demoted from the heterogeneous cache within a specified time interval. The method maintains, for the ghost cache, multiple LRU lists that designate an order in which data elements are demoted from the lower performance portion. The method utilizes the statistics to determine in which LRU lists the data elements are referenced. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: February 22, 2020
    Date of Patent: November 23, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Kyler A. Anderson, Kevin J. Ash
  • Patent number: 11169929
    Abstract: A processing device includes a core to execute instructions, and memory management circuitry coupled to, memory, the core and an I/O device that supports page faults. The memory management circuitry includes an express invalidations circuitry, and a page translation permission circuitry. The memory management circuitry is to, while the core is executing the instructions, receive a command to pause communication between the I/O device and the memory. In response to receiving the command to pause the communication, modify permissions of page translations by the page translation permission circuitry and transmit an invalidation request, by the express invalidations circuitry to the I/O device, to cause cached page translations in the I/O device to be invalidated.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: November 9, 2021
    Assignee: INTEL CORPORATION
    Inventors: Rupin Vakharwala, Amin Firoozshahian, Stephen Van Doren, Rajesh Sankaran, Mahesh Madhav, Omid Azizi, Andreas Kleen, Mahesh Maddury, Ashok Raj
  • Patent number: 11169921
    Abstract: A system and method for cache coherency within multiprocessor environments is provided. Each node controller of a plurality of nodes within a multiprocessor system receives a cache coherency protocol request from local processor sockets and other node controller(s). A ternary content addressable memory (TCAM) accelerator in the node controller determines if the cache coherency protocol request comprises a snoop request and, if it is determined to be a snoop request, searching the TCAM based on an address within the cache coherency protocol request. In response to detecting only one match between an entry of the TCAM and the received snoop request, sending a response to the requesting local processor a response without having to access a coherency directory.
    Type: Grant
    Filed: May 9, 2019
    Date of Patent: November 9, 2021
    Assignee: Hewlett Packard Enterprise Development LP
    Inventor: Frank R. Dropps
  • Patent number: 11163684
    Abstract: Provided is a predictive read ahead system for dynamically prefetching content from different storage devices. The dynamic prefetching may include receiving requests to read a first set of data of first content from a first storage device at a first rate, and requests to read a first set of data of second content from a second storage device at a different second rate. The dynamic prefetching may include determining different performance for the first storage device than the second storage device, prioritizing an allocation of cache based on a first difference between the first rate and the second rate, and a second difference based on the different performance between the storage devices, and prefetching a first amount of the first content data from the first storage device and a different second amount of the second content data from the second storage device based on the first and second differences.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: November 2, 2021
    Assignee: Open Drives, Inc.
    Inventors: Scot Gray, Sean Lee
  • Patent number: 11163465
    Abstract: A method, computer program product, and computing system for compartmentalizing a plurality of RAID extents, within a RAID system, into a plurality of rotation subgroups. A write load imbalance condition is sensed in a first rotation subgroup, chosen from the plurality of rotation subgroups, that is associated with a plurality of logical data portions. At least one of the plurality of logical data portions is moved from the first rotation subgroup to a second rotation subgroup, chosen from the plurality of rotation subgroups.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: November 2, 2021
    Assignee: EMC IP Holding Company, LLC
    Inventors: Nickolay Dalmatov, Michael P. Wahl, Jian Gao
  • Patent number: 11163468
    Abstract: Techniques for processing metadata (MD) may include: determining, in accordance with one or more criteria, a plurality of MD blocks that are similar and expected to have matching corresponding portions of MD in at least some of the plurality of MD blocks; forming a MD superblock including the plurality of MD blocks; filtering the MD superblock and generating a filtered MD superblock, wherein said filtering includes rearranging content of the MD superblock so that a first plurality of MD portions that are similar are grouped together in the filtered MD superblock, wherein at least some of the first plurality of MD portions that are similar are expected to match; and compressing the filtered MD superblock and generating a compressed filtered MD superblock. Filtering may include performing a bitshuffle algorithm that includes performing a bitwise transpose of a matrix of the MD blocks in the MD superblock.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: November 2, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Aidan O Mahony, Jason J. Duquette
  • Patent number: 11163454
    Abstract: A method, computer program product, and computing system for compartmentalizing a plurality of RAID extents, within a RAID system, into a plurality of rotation subgroups. An IO overload condition is sensed in at least one drive extent associated with a first rotation subgroup, chosen from the plurality of rotation subgroups. Instructions are provided concerning moving at least a portion of a load experienced by the first rotation subgroup to a second rotation subgroup, chosen from the plurality of rotation subgroups.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: November 2, 2021
    Assignee: EMC IP HOLDING COMPANY, LLC
    Inventors: Nickolay Dalmatov, Michael P. Wahl, Jian Gao
  • Patent number: 11163451
    Abstract: A method, computer program product, and computing system for compartmentalizing a plurality of RAID extents, within a RAID system, into a plurality of rotation subgroups. An IO load imbalance condition is sensed in a first rotation subgroup, chosen from the plurality of rotation subgroups, that is associated with a plurality of logical data portions. At least one of the plurality of logical data portions is moved from the first rotation subgroup to a second rotation subgroup, chosen from the plurality of rotation subgroups.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: November 2, 2021
    Assignee: EMC IP Holding Company, LLC
    Inventors: Nickolay Dalmatov, Michael P. Wahl, Jian Gao
  • Patent number: 11163471
    Abstract: A method, computer program product, and computing system for compartmentalizing a plurality of RAID extents, within a RAID system, into a plurality of rotation subgroups. A first logical data portion is written to a first rotation subgroup chosen from the plurality of rotation subgroups. A wear imbalance condition is sensed in a first rotation subgroup, chosen from the plurality of rotation subgroups, that is associated with a plurality of logical data portions.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: November 2, 2021
    Assignee: EMC IP Holding Company LLC
    Inventors: Nickolay Dalmatov, Michael P. Wahl, Jian Gao
  • Patent number: 11157418
    Abstract: A method for improving cache hit ratios dedicates, within a cache, a portion of the cache to prefetched data elements. The method maintains a high priority LRU list designating an order in which high priority prefetched data elements are demoted, and a low priority LRU list designating an order in which low priority prefetched data elements are demoted. The method calculates, for the high priority LRU list, a first score based on a first priority and a first cache hit metric. The method calculates, for the low priority LRU list, a second score based on a second priority and a second cache hit metric. The method demotes, from the cache, a prefetched data element from the high priority LRU list or the low priority LRU list depending on which of the first score and the second score is lower. A corresponding system and computer program product are also disclosed.
    Type: Grant
    Filed: February 9, 2020
    Date of Patent: October 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lokesh M. Gupta, Matthew G. Borlick, Beth A. Peterson, Kyler A. Anderson