Patents Examined by William F. Kraig
  • Patent number: 10796958
    Abstract: A process and resultant article of manufacture made by such process comprises forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer comprising a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer.
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: October 6, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sampath Purushothaman, Roy Rongqing Yu
  • Patent number: 10749050
    Abstract: A method for forming a back contact on an absorber layer in a photovoltaic device includes forming a two dimensional material on a first substrate. An absorber layer including Cu—Zn—Sn—S(Se) (CZTSSe) is grown over the first substrate on the two dimensional material. A buffer layer is grown on the absorber layer on a side opposite the two dimensional material. The absorber layer is exfoliated from the two dimensional material to remove the first substrate from a backside of the absorber layer opposite the buffer layer. A back contact is deposited on the absorber layer.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: August 18, 2020
    Assignee: International Business Machines Corporation
    Inventors: Richard A. Haight, James B. Hannon, Satoshi Oida
  • Patent number: 10748828
    Abstract: A fan-out sensor package includes: a redistribution portion having a through-hole and including a wiring layer and vias; a first semiconductor chip having an active surface having a sensing region of which at least a portion is exposed through the through-hole and first connection pads disposed in the vicinity of the sensing region; a second semiconductor chip disposed side by side with the first semiconductor chip in a horizontal direction and having second connection pads; dam members disposed in the vicinity of the first connection pads; an encapsulant encapsulating the redistribution portion, the first semiconductor chip, and the second semiconductor chip; and electrical connection structures electrically connecting the first connection pads and the second connection pads to the wiring layer or the vias of the redistribution portion.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: August 18, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Ha Yong Jung, Jae Kul Lee, Ji Hye Shim, Han Sang Cho, Woon Ha Choi, Jae Min Choi, Dong Jin Kim, Sung Taek Woo
  • Patent number: 10748971
    Abstract: A display apparatus including an organic light-emitting display panel and a touch sensing unit disposed on the organic light-emitting display panel is disclosed. The touch sensing unit includes a touch electrode and a wiring part connected to the touch electrode. The wiring part of the touch sensing unit passes a protruding member disposed on a non-display region of the organic light-emitting display panel, and forms a first wiring part which does not overlap the protruding member, a second wiring part overlapping the protruding part, and a connection wiring part disposed between the first and second wiring parts and having a wiring width less than the first and second wiring parts so as to overlap an edge of the protruding member.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: August 18, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Chiwook An, Miyoung Kim, Jongseok Kim, Kiho Bang
  • Patent number: 10741460
    Abstract: An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad.
    Type: Grant
    Filed: October 16, 2018
    Date of Patent: August 11, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Owen R. Fay, Kyle K. Kirby, Luke G. England, Jaspreet S. Gandhi
  • Patent number: 10741641
    Abstract: Method for forming dielectric isolation region and SiGe channels for CMOS integration of nanosheet devices generally includes epitaxially growing a multilayer structure including alternating layers of silicon, silicon germanium having a germanium content of x atomic percent and silicon germanium having a germanium content of at least 25 atomic percent greater than x. The alternating layers can be arranged and selectively patterned to form a nitride dielectric isolation region, silicon nanochannels in the NFET region, and silicon germanium nanochannels in the PFET region.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: August 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, Nicolas Loubet
  • Patent number: 10741408
    Abstract: A FinFET device structure and method for forming the same are provided. The fin field effect transistor (FinFET) device structure includes a fin structure formed over a substrate and a gate structure traversing over the fin structure. The gate structure includes a gate electrode layer which includes an upper portion above the fin structure and a lower portion below the fin structure. The upper portion has a top surface with a first width, the lower portion has a bottom surface with a second width, and the first width is greater than the second width.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chang-Yin Chen, Chai-Wei Chang, Chia-Yang Liao, Bo-Feng Young
  • Patent number: 10727199
    Abstract: An electronic device includes a circuit board, a semiconductor device package mounted on the circuit board, the semiconductor device package including a package substrate connected to the circuit board, a first semiconductor device and a second semiconductor device mounted side by side on the package substrate, and a molding surrounding a sidewall of the first semiconductor device and a sidewall of the second semiconductor device, the molding not covering a top surface of the first semiconductor device, and a heat dissipation structure on the semiconductor device package, the top surface of the first semiconductor device being in contact with the heat dissipation structure.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: July 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Yong-hoon Kim, Kil-soo Kim, Kyung-suk Oh, Tae-joo Hwang
  • Patent number: 10727113
    Abstract: A method includes providing a substrate comprising a material layer and a hard mask layer; patterning the hard mask layer to form hard mask lines; forming a spacer layer over the substrate, including over the hard mask lines, resulting in trenches defined by the spacer layer, wherein the trenches track the hard mask lines; forming a antireflective layer over the spacer layer, including over the trenches; forming an L-shaped opening in the antireflective layer, thereby exposing at least two of the trenches; filling the L-shaped opening with a fill material; etching the spacer layer to expose the hard mask lines; removing the hard mask lines; after removing the hard mask lines, transferring a pattern of the spacer layer and the fill material onto the material layer, resulting in second trenches tracking the pattern; and filling the second trenches with a conductive material.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: July 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Ethan Hsiao, Chien Wen Lai, Chih-Ming Lai, Yi-Hsiung Lin, Cheng-Chi Chuang, Hsin-Ping Chen, Ru-Gun Liu
  • Patent number: 10727375
    Abstract: A light emitting device includes a flexible substrate, at least one light emitting element, and a cover member. The flexible substrate has a first surface and a second surface, and includes a flexible base member and wiring portions disposed on a first surface side. The cover member is arranged on the second surface of the flexible substrate and defines at least a part of a recess defining an air layer. The recess is positioned so that a total maximum thickness of the flexible substrate and the cover member in a region corresponding to a region on the first surface where the at least one light emitting element is arranged is smaller than a total maximum thickness of the flexible substrate and the cover member in a region other than the region corresponding to the region on the first surface where the at least one light emitting element is arranged.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: July 28, 2020
    Assignee: NICHIA CORPORATION
    Inventor: Motokazu Yamada
  • Patent number: 10714421
    Abstract: Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a semiconductor substrate and a conductive line over the semiconductor substrate. The semiconductor device structure also includes a conductive via on the conductive line. The conductive via has an upper portion and a protruding portion. The protruding portion extends from a bottom of the upper portion towards the conductive line. The bottom of the upper portion is wider than a top of the upper portion. The semiconductor device structure further includes a dielectric layer over the semiconductor substrate, and the dielectric layer surrounds the conductive line and the conductive via.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tai-I Yang, Wei-Chen Chu, Yung-Hsu Wu, Chung-Ju Lee
  • Patent number: 10707214
    Abstract: A method of fabricating a cobalt silicide layer includes providing a substrate disposed in a chamber. A deposition process is performed to form a cobalt layer covering the substrate. The deposition process is performed when the temperature of the substrate is between 50° C. and 100° C., and the temperature of the chamber is between 300° C. and 350° C. After the deposition process, an annealing process is performed to transform the cobalt layer into a cobalt silicide layer. The annealing process is performed when the substrate is between 300° C. and 350° C., and the duration of the annealing process is between 50 seconds and 60 seconds.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: July 7, 2020
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chia-Chen Wu, Yi-Wei Chen, Chi-Mao Hsu, Kai-Jiun Chang, Chih-Chieh Tsai, Pin-Hong Chen, Tsun-Min Cheng, Yi-An Huang
  • Patent number: 10707117
    Abstract: The present disclosure teaches interconnection structures and methods for manufacturing the same.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: July 7, 2020
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Qiuhua Han, Kai Yan, Duan Yi Wu
  • Patent number: 10707241
    Abstract: An array substrate having a substrate witha bonding region on one side, the bonding region having a plurality of bonding pads arranged in order, where at least one dummy pad is provided in a first position of the bonding pads. The at least one dummy pad is used for dividing the bonding region into a plurality of bonding sub-regions, where each bonding sub-region has a plurality of bonding pads. This disclosure further provides a display panel.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: July 7, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BOE (HEBEI) MOBILE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Yuesheng Song, He Xu, Donglai Gao, Wenbo Wang, Feng Guan
  • Patent number: 10700096
    Abstract: An array substrate, a manufacturing method thereof and a display panel are provided. The array substrate includes a base substrate and a wiring layer. The base substrate includes a peripheral region, a bending region and a driving circuit region. The bending region is arranged between the driving circuit region and the peripheral region. A portion of the base substrate at the bending region is a stress buffer member arranged at an end of the bending region adjacent to the peripheral region, connected to a portion of the base substrate at the peripheral region, and spaced apart from a portion of the base substrate at the driving circuit region.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: June 30, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Peng Huang, Shuquan Yang, Wei Wang, Yanxin Wang
  • Patent number: 10685762
    Abstract: The present disclosure relates to a paste for ohmic contact to p-type semiconductor, including a metal oxide and a binder, wherein the metal oxide is a rhenium oxide or a molybdenum oxide.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: June 16, 2020
    Assignee: KOREA INSTITUTE OF SCIENCE AND TECHNOLOGY
    Inventors: Ji-Won Choi, Jin Sang Kim, Chong Yun Kang, Seong Keun Kim, Seung Hyub Baek, Sang Tae Kim, Won Jae Lee, Narendra Singh Parmar, Young-Shin Lee
  • Patent number: 10685876
    Abstract: Embodiments of the invention are directed to an interconnect stack including a first dielectric layer, a first trench formed in the first dielectric layer, and a first liner deposited in the first trench, wherein the first liner defines a second trench. A first conductive material is in the second trench and deposited over the first dielectric layer and the first conductive material. A third trench extends through the second dielectric layer and is over the first conductive material. A bottom surface of the third trench includes at least a portion of the top surface of the first conductive material. A second liner is in the third trench, on sidewalls of the third trench, and also on the portion of the top surface of the first conductive material. The second liner functions as a cap region configured to counter electro-migration or surface migration of the first conductive material.
    Type: Grant
    Filed: September 18, 2018
    Date of Patent: June 16, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Su Chen Fan, Hemanth Jagannathan, Raghuveer R. Patlolla, Cornelius Brown Peethala
  • Patent number: 10658330
    Abstract: A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: May 19, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, Yaojian Lin, Pandi C. Marimuthu
  • Patent number: 10654713
    Abstract: Methods for manufacturing MEMS structures are provided. The method for manufacturing a microelectromechanical system (MEMS) structure includes etching a MEMS substrate to form a first trench and a second trench and etching the MEMS substrate through the first trench and the second trench to form a first through hole and an extended second trench. The method for manufacturing a MEMS structure further includes etching the MEMS substrate through the extended second trench to form a second through hole. In addition, a height of the first trench is greater than ¾ of a height of the MEMS substrate, and a height of the second trench is smaller than ? of the height of the MEMS substrate.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: May 19, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chin-Han Meng, Jr-Sheng Chen, Chih-Hsien Hsu, Yu-Pei Chiang, Lin-Ching Huang
  • Patent number: 10658247
    Abstract: In accordance with some embodiments, a device includes first and second p-type transistors. The first transistor includes a first channel region including a first material of a first fin. The first transistor includes first and second epitaxial source/drain regions each in a respective first recess in the first material and on opposite sides of the first channel region. The first transistor includes a first gate stack on the first channel region. The second transistor includes a second channel region including a second material of a second fin. The second material is a different material from the first material. The second transistor includes third and fourth epitaxial source/drain regions each in a respective second recess in the second material and on opposite sides of the second channel region. The second transistor includes a second gate stack on the second channel region.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: May 19, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Chiang, Chi-Wen Liu