Abstract: A method of fabricating a semiconductor device includes etching a first surface of a semiconductor substrate from a first side using a first etching process to expose a second surface. The second surface includes a first plurality of features. The first plurality of features has an average height that is a first height. The second surface of the semiconductor substrate is etched from the first side using a second etching process to expose a third surface of the semiconductor substrate. The second etching process converts the first plurality of features into a second plurality of features. The second plurality of features has an average height that is a second height. The second height is less than the first height. A conductive layer is formed over the third surface of the semiconductor substrate using a physical deposition process.

Abstract: A semiconductor device may include a first inverter, a second inverter, a first access transistor, and a second access transistor. A drain electrode of the first access transistor or a source electrode of the first access transistor may be electrically connected to both an output terminal of the first inverter and an input terminal the second inverter. The drain electrode of the first access transistor may be asymmetrical to the source electrode of the first access transistor with reference to a gate electrode of the first access transistor. A drain electrode of the second access transistor or a source electrode of the second access transistor may be electrically connected to both an output terminal of the second inverter and an input terminal the first inverter.

Abstract: A method for aerosol-jet printing a layered perovskite structure by applying a PEDOT:PSS layer to a substrate; applying a layer of lead iodide (PbI2) to the PEDOT:PSS layer; and applying an aerosol mist of methylammonium iodide (CH3NH3I) atop the PbI2 layer with an aerosol-jet nozzle to form a CH3NH3PbI3 perovskite film layer. The substrate may be an ITO glass substrate, and the PEDOT:PSS layer may be applied by a process selected from spin-coating, inkjet-printing, slot-die-coating, aerosol-jet printing, physical vapor deposition, chemical vapor deposition, and electrochemical deposition. The PbI2 layer may be applied by a process selected from spin-coating, aerosol-jet printing, inkjet-printing, slot-die-coating, physical vapor deposition, chemical vapor deposition, and electrochemical deposition, and the PbI2 for application to the PEDOT:PSS layer may be in a solution of DMF, DMSO, ?-butyrolactone, or a combination thereof.

Abstract: Dual-base two-sided bipolar power transistors which use an insulated field plate to separate the emitter/collector diffusions from the nearest base contact diffusion. This provides a surprising improvement in turn-off performance, and in breakdown voltage.

Abstract: A bonding between a first substrate and a second substrate, the method includes the steps of: a) providing the first substrate and the second substrate, b) forming a first bonding layer having tungsten oxide on the first substrate and a second bonding layer having tungsten oxide on the second substrate, at least one of the first bonding layer and of the second bonding layer including a third element M so as to form an MWxOy-type alloy, the atomic content of M in the composition of the alloy being between 0.5 and 20% and preferably between 1 and 10%, c) carrying out a direct bonding between the first bonding layer and the second bonding layer, and d) performing a heat treatment at a temperature greater than 250° C.

Abstract: A mask layer is formed over a semiconductor device. The semiconductor device includes: a gate structure, a first layer disposed over the gate structure, and an interlayer dielectric (ILD) disposed on sidewalls of the first layer. The mask layer includes an opening that exposes a portion of the first layer and a portion of the ILD. A first etching process is performed to etch the opening partially into the first layer and partially into the ILD. A liner layer is formed in the opening after the first etching process has been performed. A second etching process is performed after the liner layer has been formed. The second etching process extends the opening downwardly through the first layer and through the gate structure. The opening is filled with a second layer after the second etching process has been performed.

Abstract: A light emitting device includes a flexible substrate, at least one light emitting element, a sealing resin, an adhesion layer and a support member. The flexible substrate includes a flexible base member and a plurality of wiring portions disposed on one surface of the base member. At least one light emitting element is arranged on a first surface of the flexible substrate and electrically connected to the wiring portions. The sealing resin seals the at least one light emitting element. The adhesion layer and the support member are arranged in this order on a second surface of the flexible substrate different from the first surface of the flexible substrate. The support member has a recess in a region corresponding at least to a region on the first surface where the at least one light emitting element is arranged.

Abstract: Semiconductor device structures are provided. The semiconductor device structures include a semiconductor substrate. The semiconductor device structures also include an inner metal layer disposed on the semiconductor substrate and a top metal layer disposed on the inner metal layer, wherein the top metal layer has a first portion and a second portion, and wherein the first portion completely covers the inner metal layer, the second portion surrounds the first portion, and the first portion is separated from the second portion. The semiconductor device structures further include a passivation layer disposed on the top metal layer, wherein the passivation layer has a hollowed pattern to expose the top metal layer.

Abstract: A method of forming a semiconductor package comprises forming one or more first vias in a first side of a substrate and attaching a first side of a first microelectronic element to the first side of the substrate. The first microelectronic element is electrically coupled to at least one of the one or more first vias. The method further comprise obtaining a second microelectronic element including one or more second vias in a first side of the second microelectronic element, and attaching a second side of the substrate to the first side of the second microelectronic element. The second microelectronic element is electrically coupled to at least one of the one or more first vias. Each of one or more connecting elements has a first end attached to a first side of the second microelectronic element and a second end extends beyond a second side of the first microelectronic element.

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to vertical channel devices and a method of making the same. In one aspect, a method of forming vertical channel devices includes forming a first vertical channel structure extending from a first bottom electrode region and a second vertical channel structure extending from a second bottom electrode region. The first and the second vertical channel structures protrude from a dielectric layer covering the first and second bottom electrode regions. The method additionally comprises forming a first hole exposing the first bottom electrode region and a second hole exposing the second bottom electrode region, where the first and the second holes extending vertically through the dielectric layer. The method additionally includes forming a conductive pattern including a set of discrete pattern parts on the dielectric layer.

Abstract: The invention relates to an optoelectronic component. The component includes a semiconductor layer sequence having an active layer that is designed to emit electromagnetic radiation during operation of the component, at least one current-spreading layer on a radiation outlet surface of the semiconductor layer sequence, wherein the current-spreading layer is connected to a contact structure in an electrically conductive manner by means of an adhesion layer. The adhesion layer comprises a titanium oxide, wherein in the titanium oxide the oxygen has the oxidation state W0, with W0=?2, and the titanium has the oxidation state WT, with 0 <WT<+4.

Abstract: A lead frame includes an electrode, a hanger lead, and an outer frame and is formed integrally with a supporting member supporting the electrode, so that a package having a depression in which a light-emitting element will be mounted is formed. The depression is open on the upper side, its side walls are mainly constituted of the supporting member, and at least a part of its bottom surface includes the electrode. The electrode is disposed in a supporting member forming region. The hanger lead extends from the outer frame to reach the supporting member forming region. A chamfered surface is formed on at least a part of an upper side corner of an end of the hanger lead.

Abstract: A photovoltaic device, particularly a solar cell, comprises an interface between a layer of Group III-V material and a layer of Group IV material with a thin silicon diffusion barrier provided at or near the interface. The silicon barrier controls the diffusion of Group V atoms into the Group IV material, which is doped n-type thereby. The n-type doped region can provide the p-n junction of a solar cell in the Group IV material with superior solar cell properties. It can also provide a tunnel diode in contact with a p-type region of the III-V material, which tunnel diode is also useful in solar cells.

Abstract: Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. A barrier layer stack including a crystalline electrically conductive barrier layer and an amorphous barrier layer is formed in the backside recesses prior to formation of a metal fill material layer.

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

Abstract: Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. An electrically conductive, amorphous barrier layer can be formed prior to formation of a metal fill material layer to provide a diffusion barrier that reduces fluorine diffusion between the metal fill material layer and memory films of memory stack structures. The electrically conductive, amorphous barrier layer can be an oxygen-containing titanium compound or a ternary transition metal nitride.

Abstract: An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

Abstract: The method for manufacturing a crystalline silicon substrate for a solar cell includes: forming a texture on the surface of a single-crystalline silicon substrate by bringing an alkali solution and the surface of the single-crystalline silicon substrate into contact with each other; bringing an acidic solution and the surface of the single-crystalline silicon substrate into contact with each other to perform an acid treatment thereon; and then by bringing ozone water and the surface of the single-crystalline silicon substrate into contact with each other to perform an ozone treatment thereon. One aspect of embodiment is that the acidic solution used for the acid treatment is hydrochloric acid. Another aspect of embodiment is that the ozone treatment is performed by immersing the single-crystalline silicon substrate into the ozone water bath.

Abstract: Provided herein is a method for producing hollow contact areas for insertion bonding, formed on a semiconductor substrate comprising a stack of one or more metallization layers on a surface of the substrate. Openings are etched in a dielectric layer by plasma etching, using a resist layer as a mask. The resist layer and plasma etch parameters are chosen to obtain openings with sloped sidewalls having a pre-defined slope, due to controlled formation of a polymer layer forming on the sidewalls of the resist hole and the hollow contact opening formed during etching. According to a preferred embodiment, metal deposited in the hollow contact areas and on top of the dielectric layer is planarized using chemical mechanical polishing, leading to mutually isolated contact areas. The disclosure is also related to components obtainable by the method and to a semiconductor package comprising such components.

Abstract: An array substrate and a fabrication method thereof, and a display device are provided. The array substrate comprises a lining substrate and an electrode pattern formed on the lining substrate, and the electrode pattern includes a plurality of strip-shaped electrodes. There are a plurality of strip-shaped protrusions on an upper surface of the lining substrate, and at least part of strip-shaped electrodes among the plurality of strip-shaped electrodes are formed on the strip-shaped protrusions one-to-one; and there is an included angle between an extending direction of the strip-shaped electrodes and an extending direction of the strip-shaped protrusions, and the included angle is configured so that a rubbing direction of an alignment film is along the extending direction of the strip-shaped protrusions.