Abstract: An array substrate having a substrate witha bonding region on one side, the bonding region having a plurality of bonding pads arranged in order, where at least one dummy pad is provided in a first position of the bonding pads. The at least one dummy pad is used for dividing the bonding region into a plurality of bonding sub-regions, where each bonding sub-region has a plurality of bonding pads. This disclosure further provides a display panel.

Abstract: A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die.

Abstract: A packaged semiconductor device includes: a substrate; an semiconductor die attached to a top surface of the substrate; a mold body surrounding the semiconductor die; a tiered through mold via (TMV) comprising: a first recess having a recessed surface within the mold body at a first depth, and a second recess from the recessed surface to a second depth that exposes a ground contact area on a bonding area on the top surface of the substrate, wherein the first depth is greater than the second depth; and a metal shielding layer formed on a top surface of the mold body to form a shielded mold body, wherein the metal shielding layer makes direct contact with at least one sidewall of the first recess, with at least a portion of the recessed surface, with at least one sidewall of the second recess, and with the ground contact area.

Abstract: A method of manufacturing a multi-layer wafer is provided. At least one stress compensating polymer layer is applied to at least one of two heterogeneous wafers. The stress compensating polymer layer is low temperature bonded to the other of the two heterogeneous wafers to form a multi-layer wafer pair. Channels are created between die on at least one of the two heterogeneous wafers. The channels are back filled with one of oxide or polymer to create a channel oxide deposition.

Abstract: A process includes forming through vias needed to connect a bottom device layer in a bottom silicon wafer to the one in the top device layer in a top silicon wafer including a silicon-on-insulator (SOI) wafer. Through vias are disposed in such a way that they extend from the middle of the line (MOL) interconnect of the top wafer to the buried oxide (BOX) layer of the SOI wafer with appropriate insulation provided to isolate them from the SOI device layer. A resultant article of manufacture is also disclosed.

Abstract: A method of manufacturing a light emitting element includes: providing a wafer that includes a substrate having a first principal face and a second principal face, a dielectric multilayer film disposed on the first principal face, and a semiconductor structure disposed on the second principal face; forming modified regions in the substrate by focusing a laser beam inside the substrate via the dielectric multilayer film, and allowing cracks to form from the modified regions to the dielectric multilayer film; subsequent to forming the modified regions in the substrate, removing regions of the dielectric multilayer film that contain cracks; and cleaving the wafer along regions where cracks were formed in the substrate.

Abstract: A semiconductor sensor, comprising a gas-sensing device and an integrated circuit electrically connected to the gas-sensing device, is provided. The gas-sensing device includes a substrate having a sensing area and an interconnection area in the vicinity of the sensing area, an inter-metal dielectric (IMD) layer formed above the substrate in the sensing area and in the interconnection area, and an interconnect structure formed in the interconnection area. The interconnect structure includes a tungsten layer buried in the IMD layer, wherein part of a top surface of the tungsten layer is exposed by at least a via. The interconnect structure further includes a platinum layer formed in said at least the via, wherein the platinum (Pt) layer directly contacts the top surface of the tungsten layer.

Abstract: A method of generating a layout and manufacturing a semiconductor device, including receiving a design layout of a semiconductor device including active fins; extracting a design rule of the active fins from the design layout; forming fin lines overlapping the active fins such that the fin lines have a length that is greater than a length of the active fins, wherein the fin lines continuously extend from a position adjacent to one edge of a layout region of the semiconductor device toward another edge, and are formed in an entirety of the layout region of the semiconductor device; forming a mandrel pattern layout in an entirety of the layout region of the semiconductor device, using the fin lines; and forming a cut pattern layout in the entirety of the layout region of the semiconductor device, using the active fins.

Abstract: A light emitting device includes a substrate; a light emitting element mounted on an upper surface of the substrate; a light-reflecting member surrounding lateral surfaces of the light emitting element; and a sealing member disposed over an upper surface of the light emitting element and an upper surface of the light-reflecting member. An outer edge of the upper surface of the light-reflecting member coincides with an outer edge of a lower surface of the sealing member.

Abstract: A method for making a semiconductor device may include forming at least one memory array including a plurality of recessed channel array transistors (RCATs) on a substrate, and forming periphery circuitry adjacent the at least one memory array and comprising a plurality of complementary metal oxide (CMOS) transistors on the substrate. Each of the CMOS transistors may include spaced-apart source and drain regions in the substrate and defining a channel region therebetween, and a first superlattice extending between the source and drain regions in the channel region. The first superlattice may include a plurality of stacked groups of layers, with each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. A gate may be over the first superlattice and between the source and drain regions.

Abstract: Provided is a method of fabricating a semiconductor package. The method includes preparing a package substrate having a substrate pad, and mounting a semiconductor chip on the substrate pad. Mounting the semiconductor chip includes forming a resin layer containing a solder and reducing agent granules having a first capsule layer, between a chip pad of the semiconductor chip and the substrate pad, and bonding the chip pad to the substrate pad using laser irradiated to the semiconductor chip.

Abstract: A method includes forming a gate stack of a transistor. The formation of the gate stack includes forming a silicon oxide layer on a semiconductor region, depositing a hafnium oxide layer over the silicon oxide layer, depositing a lanthanum oxide layer over the hafnium oxide layer, and depositing a work-function layer over the lanthanum oxide layer. Source/drain regions are formed on opposite sides of the gate stack.

Abstract: A method of making thin film transistor including: forming a gate electrode, forming a gate insulating layer on the gate electrode; locating a semiconductor layer on the gate insulating layer; placing stripe-shaped masks on the semiconductor layer, wherein the thickness of the stripe-shaped masks is H, the spacing distance between the stripe-shaped masks is L; depositing a first conductive film layer along a first direction, the thickness of the first conductive film layer is D, a first angle between the first direction and a direction along the thickness of the stripe-shaped masks is ?1, ?1<tan?1(L/H); depositing a second conductive film layer along a second direction, a second angle between the second direction and the direction along the thickness of the stripe-shaped masks is ?2, ?2<tan?1[L/(H+D)], 0<Htan?1+(H+D)tan?2?L<10 nm, the first conductive film layer forms a source electrode, the second conductive film layer forms a drain electrode.

Abstract: A method of making nanoscale channels including: providing a substrate, locating a photoresist mask layer on the substrate, the thickness of the photoresist mask layer equals H; forming a patterned mask layer by exposing and developing the photoresist mask layer, the patterned mask layer includes a plurality of parallel and spaced stripe masks, the spacing between adjacent stripe masks equals L; depositing a first thin film layer on the substrate in a first direction, the thickness of the first thin film layer equals D, a first angle between the first direction and a direction in the thickness of the stripe masks equals ?1, ?1<tan?1(L/H); depositing a second thin film layer on the substrate in a second direction, a second angle between the second direction and the direction in the thickness of the stripe masks equals ?2, ?2<tan?1[L/(H+D)], 0<Htan?1+(H+D)tan?2?L<10 nm.

Abstract: An organic light emitting display device includes a substrate with a first emitting region adjacent a second emitting region, a first anode in the first emitting region, a first organic light emitting layer on the first anode, a second anode in the second emitting region, and a second organic light emitting layer on a part of the first anode and the second anode. The second organic light emitting layer includes a material different from the first organic light emitting layer.

Abstract: A method of manufacturing a LIDAR chip and applying an anti-reflection (AR) coating to a coupling structure of the LIDAR chip. The coupling structure if formed on a wafer. A pocket is formed in the wafer adjacent the coupling structure. The AR material is deposited on top of the wafer and coupling structure. The AR material is etched to form the AR coating on the coupling structure.

Abstract: A first light-emitting element and a second light-emitting element that have a resonance structure that causes output light from a light-emission functional layer to resonate between a reflective layer and a semi-transmissive reflective layer, and a pixel definition layer, and in which an aperture part is formed to correspond to each of the first light-emitting element and the second light-emitting element, are formed on a base. A first interval between the reflective layer and the semi-transmissive reflective layer in the first light-emitting element and a second interval between the reflective layer and the semi-transmissive reflective layer in the second light-emitting element are different, and a film thickness of the pixel definition layer is less than a difference between the first interval and the second interval.

Abstract: A semiconductor device manufacturing method includes forming a first mask over a semiconductor substrate including a first and second surfaces and an electrode provided on the second surface side, forming a first part having tapered shape by etching the semiconductor substrate with the first mask as a mask, forming a second mask covering a side surface of the first part and exposing the bottom surface of the first part, forming a second part reaching the electrode by etching the semiconductor substrate with the second mask as a mask, forming an insulating film covering the side surfaces of the first and second parts, and forming a conductive member connected to the electrode in the first and second parts. A difference between a maximum width and a minimum width of the second part is smaller than a difference between a maximum width and a minimum width of the first part.

Abstract: Devices and techniques are disclosed herein which include a first LED device layer, a second LED device layer, and an adhesive bondline disposed between the first LED device layer and the second LED device layer. The adhesive bondline includes a bondline thickness, a plurality of spacers disposed within the adhesive bondline, and a silicone matrix. The plurality of spacers may have a diameter or a shortest axis between 0.5 and 10 micrometers and the coefficient of variation is 10% or less. The plurality of spacers may be include SiO2, alumina, soda lime glass, may be inorganic, or polymeric.

Abstract: Dual-base two-sided bipolar power transistors which use an insulated field plate to separate the emitter/collector diffusions from the nearest base contact diffusion. This provides a surprising improvement in turn-off performance, and in breakdown voltage.