Abstract: A method for growing Silicon On Insulator (SOI) films using only conventional very large scale integration (VLSI) techniques is provided. By sequentially varying the flow of HCL gas during the vertical-growth, lateral-overgrowth, coalescence, and planarization stages of the epitaxial deposition process allows the formation of high-quality SOI films on wider oxide stripes suitable for general transistor applications.

Abstract: The purity and perfection of a semiconductor is improved by depositing a patterned mask (12) of a material impervious to impurities of the semiconductor on a surface (14) of a blank (10). When a layer (40) of semiconductor is grown on the mask, the semiconductor will first grow from the surface portions exposed by the openings (16) in the mask (12) and will bridge the connecting portions of the mask to form a continuous layer (40) having improved purity, since only the portions (42) overlying the openings (16) are exposed to defects and impurities. The process can be reiterated and the mask translated to further improve the quality of grown layers.

Abstract: Base resistance in an integrated injection logic cell is reduced by providing a low resistance conductive path over the device cell and contacting the base regions of vertical transistors in the cell. In fabricating the I.sup.2 L cell a first intrinsic polysilicon layer is formed over the surface of the device cell, and N-type dopant is diffused through the polysilicon layer to form the N+ collectors of the NPN vertical transistors. Silicon oxide is formed over the doped polysilicon and the undoped intrinsic polysilicon is then removed. Exposed edge portions of the N doped polysilicon is then oxidized to completely insulate the surface of the polysilicon. A second layer of intrinsic polysilicon is then formed over the device cell and P type dopant is diffused through the second polysilicon layer to form the emitter and collector of a lateral PNP transistor and to contact the base regions of the NPN vertical transistors between the N+ collectors.

Abstract: A method of recovering intact at room temperature a layer of a first material, such as silicon carbide, produced by depositing it from the gas phase at a deposition temperature above room temperature on a substrate of a second material, such as silicon, having a different coefficient of thermal expansion than that of the first material. The substrate is separated from the layer prior to cooling, and then the separated layer is cooled to room temperature free of stresses otherwise present as a result of the different thermal expansions of the substrate and layer.

Abstract: A method for manufacturing a semiconductor device, comprising the steps of selectively oxidizing a surface of a semiconductor layer of a first conductivity type so as to form a field oxide film, selectively forming an impurity region of a second conductivity type in an element region isolated by the field oxide film, forming a polycrystalline silicon pattern containing an impurity of the first conductivity type on a surface including at least part of the impurity region and the field oxide film, and diffusing the impurity of the first conductivity type from the polycrystalline silicon pattern into the impurity region so as to form another impurity region of the first conductivity type contiguous with the field oxide film, wherein a thickness t of the field oxide film and a concentration n of the impurity of the first conductivity type in the polycrystalline silicon pattern have the following relation:t (.mu.m).ltoreq.-0.117.times.10.sup.-20 (.mu.m.multidot.cm.sup.3).multidot.n(cm.sup.-3)+1.42 (.mu.m)for 1.

Abstract: There is provided a method of producing inorganic thin films by metal inorganic chemical vapor deposition. The method comprises forming a vapor stream comprising a vapor mixture of an organometallic compound and a heterocyclic organic compound incorporating a group V or group VI element, and thermally decomposing the mixture on a heated substrate to form an inorganic layer. The heterocyclic compound may be an aliphatic or aromatic ring compound. The mixture may include vapors appropriate for deposition of ternary or higher order compounds, and/or for introducing dopants.

Abstract: A method for fabricating a semiconductor structure which reduces substrate current injection from lateral bipolar transistors. A buried layer of a first conductivity type is formed in a semiconductor substrate of opposite conductivity. An epitaxial layer of the first conductivity type is formed such that at least a portion of the epitaxial layer overlies the buried layer. Isolation oxide regions are formed in a epitaxial layer. The isolation oxide regions extend to the substrate to define an island of electrically isolated epitaxial material. A selected impurity of the first conductivity type is introduced into that portion of the epitaxial layer beneath the to-be-formed lateral transistor. The lateral transistor is formed in the epitaxial layer.

Abstract: A method for trench isolation of a silicon island for device fabrication using only conventional very large scale integration (VLSI) techniques is provided. The combination of the sidewall isolation achieved with the trench isolation and the underlying oxide film create a totally dielectrically isolated structure without the possibility of latch-up between adjacent devices.

Abstract: A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different etch characteristics permits selective oxidation of desired portions only of the structure without need for masking and removal of selected material from desired locations by batch removal processes again without use of masking. There results VLSI circuits having increased density and reliability.

Abstract: A semiconductor device has a diffused layer of a first conductivity type which extends to a buried layer of a second conductivity type, formed in a manner to extend from a part of a surface of a semiconductor layer of the second conductivity type which is epitaxially grown on a semiconductor substrate of the first conductivity type through the buried layer of the second conductivity type. A semiconductor junction capacitance is formed of the diffused layer of the first conductivity type and the buried layer of the second conductivity type, and the concentration of an impurity to be introduced into the buried layer of the second conductivity type is controlled.

Abstract: A CMOS process is described which is particularly suited for forming dynamic memory cells. The cells are formed in an n-well and a single plate member formed from a first layer of polysilicon is used for the entire array. Unique etching of the first polysilicon layer prevents stringers from occurring when the second layer of polysilicon is deposited. A tri-layer dielectric is used for the capacitors in the array. Novel "rear-end" processing is disclosed using a phosphorus doped glass.

Abstract: A reduced pressure epitaxial deposition method is disclosed to maximize performance and leakage limited yield of devices formed in the epitaxial layer. The method includes specified prebake and deposition conditions designed to minimize arsenic (buried subcollector) and boron (buried isolation) autodoping effects when pressures below one atmosphere are selected in accordance with the subcollector-to-isolation area ratio.

Abstract: The present invention provides for the deposition of group III-V ternary epitaxial films onto the surfaces of suitable semiconductor substrates. The deposition is accomplished by a vapor phase epitaxy-hydride technique using a group III binary alloy as a group III metal source and phosphine, arsine or stibine as a group V hydride source.

Abstract: In intermetallic semiconductor crystal growth such as the growth of GaAs and GaAlAs, silicon as a dopant can be introduced more efficiently and evenly when provided as a gaseous hydride based compound involving a molecule where there are joined silicon atoms such as Si.sub.2 H.sub.6 to Si.sub.5 H.sub.12.

Abstract: A method of making an electrically-programmable memory array in which the memory elements are capacitor devices formed in anisotropically etched V-grooves, providing enhanced dielectric breakdown at the apex of the groove. After breakdown, a memory element exhibits a low resistance to a grounded substrate. The method includes forming access transistors in series with the memory elements, and polycrystalline silicon, deposited to form control gates of the access transistors, also forms address lines. Oxide is formed in the V-groove thinner than the gate oxide thickness formed for the access transistor, providing a lower programming voltage. These factors provide a very small, high speed device.

Abstract: Dielectrically isolated single crystal silicon of high quality is produced by an extremely convenient process. This process involves the fusing of two silicon bodies where at least one of these bodies has a region of silicon oxide. The bodies are contacted so that the silicon oxide is at an interface between the two bodies. The bodies are then heated to an elevated temperature while applying a nominal electrical potential across the interface. This combination of applied potential and temperature permanently fuses the two bodies without producing any significant damage to the crystal quality of these bodies.

Abstract: A method of fabricating gallium arsenide devices in which contact isolation is provided by a deep mesa step structure. Step coverage of deposited conductive films is facilitated by preferential orientation of the non-centrosymmetric crystal substrate and wet anisotropic etching that provides a sloped step. Problems of fine line definition of the Schottky anode contact in the photolithographic process are addressed by a two-step exposure of a single layer of thick photoresist followed by a chlorobenzene soak prior to development that ensures a retrograde resist profile needed for good lift-off of undesired evaporated metal. Mesas as deep as 7 .mu.m have been obtained, which permit the fabrication of monolithic planar mixer millimeter-wave diodes with low series resistance and reduced parasitic capacitance.

Abstract: An n.sup.- silicon layer is epitaxially grown on an oxide film with predetermined openings disposed on one main face of an N.sup.+ silicon substrate to form single crystalline portions on the openings and polycrystalline portions on the oxide film. Ion implantation and thermal annealing is used to convert the polycrystalline portions to P.sup.+ external base regions and form P.sup.+ internal base regions in the single-crystalline portions. Arsenic ions are selectively implanted into the internal base regions to form n.sup.+ emitter regions. Then, base and emitter electrodes are formed on the external base and emitter regions to be electrically insulated from one another by an oxide film and a collector electrode is formed on the other main face of the substrate.

Abstract: Manufacture of bipolar substantially isoplanar integrated circuit structures is accomplished by rearrangement of the conventional masking steps and by the substitution and full integration of implanting methods for diffusion methods. A uniform nitride layer is deposited over the basic structure of epitaxial islands separated by isolation oxide regions thereby passivating and protecting the isolation oxide regions, epitaxial oxide buffer layer and epitaxial layer from environmental contaminants. The nitride layer which forms part of a composite protective layer is maintained in place throughout a major portion of the fully integrated sequential implanting steps during which the collector sink, base and emitter regions are introduced into the epitaxial islands. At least a portion of the composite protective layer is a barrier to environmental contaminants throughout the process. The overall number of steps is reduced, etching steps minimized, and overall reliability of the structure improved.

Abstract: Light-controlled thyristor, including a semiconductor body having a surface, a first zone being of a given conduction type and having a given depth and being adjacent to the surface of the body, a second zone of the given conduction type having a region intended for exposure, a third zone of a conduction type opposite to the given type being disposed under the first and second zones and having a part thereof emerging to the surface of the body between the first and second zones and having a depression formed therein containing the region intended for exposure, electrodes contacting the first and second zones, said second zone having a first and a second subzone, the first subzone having the given depth and being disposed between the part of the third zone emerging to the surface of the body and the depression, the first subzone being in contact with one of the electrodes, the second subzone being the region intended for exposure in the depression and being formed by implanted ions, the second subzone being di