Abstract: A process improvement for enabling the development of low cost transistor devices, particularly MOS FETs, in annealed polysilicon formed on an insulator; the improvement resulting from the use of silicon ribbons as substrates.

Abstract: Method for manufacturing a fast bipolar transistor, including a semiconductor body having a transistor formed therein including a base contact, an emitter zone, and a base zone, the base zone being subdivided into a first inner subregion disposed below the emitter zone and a second outer subregion including all other base regions and being disposed below the base contact, each of the subregions being separately doped to a given degree. The method for manufacturing the same includes the application of a layer of undoped polysilicon on top of a monocrystalline silicon substrate, and subsequently doping the polysilicon by ion implantation with one or more dopants, such as boron or arsenic, followed by a diffusion process for thermally diffusing the dopants into the silicon substrate, thereby creating emitter and base regions that are very small and thin, so that high frequency operation of the resulting transistor may be attained.

Abstract: Semiconductor doping compositions comprising a suspension of (a) a dopant material, in the form of finely divided spherical particles of narrow size distribution from about 0.1 D to D, where D is the diameter of the largest particle and is no more than about (1.mu.) comprising a member selected from the group consisting of B.sub.x Si.sub.y, B.sub.x N.sub.y, P.sub.x Si.sub.y, P.sub.x N.sub.y, As.sub.x Si.sub.y and Sb.sub.x Si.sub.y wherein x and y vary from about 0.001 to about 99.999 mole percent, (b) an effective amount of a thermally degradable polymeric organic binder such as polymethyl methacrylate; and (c) an amount of an organic solvent, such a cyclohexanone, sufficient to dissolve said polymeric organic binder, such as polymethylmethacrylate, and to disperse said dopant material are disclosed.

Abstract: A process for depositing an epitaxial film of a III-V compound onto the surface of a crystallographically compatible substrate which includes contacting said substrate with a vaporous mixture of a group III element and a group V element to effect the deposition of a group III-V compound thereon while simultaneously introducing a flow of hydrogen halide gas during deposition of the group III-V compound.

Abstract: A method of manufacturing a semiconductor integrated circuit of the BI-MOS type on a common semiconductor substrate comprising forming an oxide film by thermal oxidation to isolate the elements and a base layer of one conductivity type by a surrounding dielectric followed by removing the oxide film from emitter and collector electrode extending regions. A silicon film of a second conductivity type is formed by patterning and used to form an emitter layer and a collector extending layer by differing impurities from the silicon film. Patterning is then employed to form gate, emitter and collector electrodes. Finally, the mask for the silicon film is used to form a base electrode extending layer, a source layer and a drain layer of the first conductivity type and of high impurity density.

Abstract: A method for depositing a (Hg,Cd)Te film onto a CdTe substrate by using two separate vaporizeable sources of reactant materials each maintained at separate and distinct temperatures followed by the step of mixing both of each sources with a hydrogen halide gas and passing the resulting mixtures over a CdTe substrate maintained at a lower temperature distinct and different from the temperatures maintained during vaporization of the two distinct vaporizeable sources.

Abstract: A method of forming a semiconductor device having a single crystal silicon substrate, the surface of which includes exposed silicon areas bounded by and coplanar with insulating oxide regions. A polysilicon layer is deposited thereon and annealed to form a single crystal epitaxial region overlying the exposed substrate areas while the regions overlying the oxide areas in the substrate surface may be of polycrystalline form. This structure is applied to NMOS, CMOS, MESFET, and I.sup.2 L devices to achieve high packing density, high speed, improved isolation between devices and reduced susceptibility to latch-up.

Abstract: Disclosed is a method of making on a common substrate complementary vertical NPN and PNP transistors having matched high performance characteristics. A barrier region of a first conductivity type is formed on a semiconductor substrate of a second conductivity type. Then, a collector region for one of the complementary transistors of a second conductivity type is formed within the barrier region. It is convenient to simultaneously form isolation regions of a second conductivity type in the substrate while forming the collector region. A collector region of a first conductivity type is then formed in the substrate for the other of the complementary transistors. An epitaxial layer of semiconductor material doped with ions of the first conductivity type is then formed on the surface of the substrate.In a preferred embodiment the P-type emitter for the PNP transistor is formed prior to a last drive-in treatment by forming a polycrystalline silicon layer on the exposed surface of the base.

Abstract: A method for forming a Bi-CMOS structure, wherein a vertical npn transistor and CMOS transistors are formed on a single semiconductor substrate, is disclosed. After forming a p-type epitaxial silicon layer on a p-type silicon substrate with a plurality of n.sup.+ -type buried layers therein, n-type wells are formed to extend to the n.sup.+ -type buried layers. Selective oxidation is performed to form field oxide films so as to define an n-type element region for the npn transistor, an n-type element region for the p-channel MOS transistor, and a p-type element region for the n-channel MOS transistor. An oxide film as a gate oxide film for the CMOS is formed on the surfaces of all the element regions. After forming a p-type active base region of the npn transistor by ion-implantation of boron, an emitter electrode comprising an arsenic-doped polysilicon layer is formed in contact with the p-type active base region.

Abstract: A process is provided for manufacturing bi-polar transistors integrated on silicon. To form transistors of very small dimensions, a layer of polycrystalline silicon is deposited (after a localized oxidization step) which is etched and which is doped so as to serve as doping source for P.sup.+ extrinsic base regions of the transistor. After doping of the P intrinsic base, the oxide and/or nitride is then deposited at low pressure which is implanted with an impurity facilitating dissolution thereof. On the vertical walls of the polycrystalline silicon around the base, the nitride is not dissolved. Elsewhere it is easily dissolved. Advantage is taken of the oxide or nitride thickness which remains to form by diffusion of an N.sup.+ emitter region which will not extend laterally as far as the P.sup.+ type extrinsic base but which will allow to remain an intrinsic base of very small thickness. The emitter diffusion may take place through a second polycrystalline silicon layer.

Abstract: A method for fabricating a three-dimensional multi-layer integrated circuit of single crystalline CeO.sub.2 and Si is proposed.This method is characterized in that a single crystalline CeO.sub.2 insulation layer, or the like, is formed on a single crystalline Si substrate. An isolation region is formed in the single crystalline Si substrate. The region is transformed into a SiO.sub.2 insulation layer by selectively introducing oxygen ions through the single crystalline CeO.sub.2 insulation layer and reacting the oxygen ions with the single crystalline Si.An epitaxial growth single crystalline Si layer is formed on the single crystalline CeO.sub.2 insulation layer.Predetermined processes, such as forming a single crystalline CeO.sub.2 layer, are performed thereafter to form the three-dimensional structures of semiconductor elements such as MOS transistors and bipolar transistors with high packing density and reliability.

Abstract: A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices. The use of materials in successive layers having different etch characteristics permits selective oxidation of desired portions only of the structure without need for masking and removal of selected material from desired locations by batch removal processes again without use of masking. There results VLSI circuits having increased density and reliability.

Abstract: In a process for producing a semiconductor device, having a thick silicon oxide layer, on an isolation region, an oxide layer is selectively formed on an area for providing the isolation region of the epitaxial layer. Then an anti-oxidation masking layer is selectively formed on the oxide layer. The semiconductor substrate is selectively oxidized using the anti-oxidation masking layer for forming the thick silicon oxide layer. The anti-oxidation masking layer on the silicon oxide layer, which corresponds to the area for providing the isolation region, is removed and impurities are introduced into the area for providing the isolation region. Then the semiconductor substrate is oxidized in an oxidizing atmosphere so that the impurities are activated to form an isolation region and an oxide layer on the isolation region, the oxide layer having an increased thickness. The thus-obtained thick silicon dioxide layer makes the parasitic capacitance between the conductive lines and the isolation region small.

Abstract: An electroluminescent semiconductor device comprising bodies of conductive and resistive crystalline gallium nitride (GaN) which are successively epitaxially deposited on a surface of a heat-treated sapphire substrate, and a body of insulative crystalline gallium nitride epitaxially deposited on the resistive body.

Abstract: A self-aligned metal process and resulting structure is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. All gate electrodes are composed of polysilicon while the remaining contacts are composed of metal. The insulation between the metal contacts and the polysilicon is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The method involves providing a silicon body and then forming a first insulating layer on a major surface of the silicon body. A first layer of polysilicon is formed thereover. Openings are made in the polysilicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. The openings are in those areas designated to be the gate regions of the field effect transistors in the integrated circuit.

Abstract: Disclosed is a method for manufacturing a semiconductor device of high reliability, high performance and high integration with high yield. The method of this invention has the steps of forming at least one groove in a semiconductor substrate, forming a non-single-crystalline semiconductor film to cover an entire surface of the semiconductor substrate including an inner surface of the groove, selectively etching the non-single-crystalline semiconductor film so as to leave the non-single-crystalline semiconductor film on at least a side wall of the groove, and forming an oxide isolation layer in the groove by thermal oxidation.

Abstract: An apparatus for and a method of making heterojunction source-drain insulated gate field-effect transistors in order to obtain higher gain-bandwidth products at microwave frequencies. A semi-insulating InP semiconductor substrate is provided with a ternary alloy layer of p-type Ga.sub.0.47 In.sub.0.53 As, or optionally, an acceptor-doped p-type bulk of Ga.sub.0.47 In.sub.0.53 As can be substituted. Troughs are shaped in the substrate and layer for receiving a material lattice-matched to the n.sup.+ p-type Ga.sub.0.47 In.sub.0.53 As to perform as the source and drain contacts, n.sup.+ doped InP might be a suitable material. An optional method for forming the contacts calls for directing a stream of phosphine and hydrogen onto source and drain contact windows contacting the Ga.sub.0.47 In.sub.0.53 As which is heated to 750.degree. C. for about 15 minutes. This creates graded heterojunction source and drain contacts having a lattice-matching variable composition.

Abstract: A method of fabricating semiconductor devices on semi-insulating GaAs substrates is provided. Pre-etched holes in the substrate are covered with a dielectric which is etched to expose the substrate only at the bottom of the holes. Epitaxial growth of active GaAs in the holes may then proceed with a single crystallographic orientation. The dielectric covering the sidewalls of the holes prevents unwanted random growth and poor surface morphology of the active area.

Abstract: A process for producing VLSI (very large scale integrated) circuits employs techniques of self-aligned gates and contacts for FET devices and for both diffused conducting lines in the substrate and polysilicon conducting lines situated on isolating field oxide formed on the substrate. Mask alignment tolerances are increased and rendered non-critical. The use of materials in successive layers having different etch characteristics permits selective oxidation of desired portions only of the structure without need for masking and removal of selected material from desired locations by batch removal processes again without use of masking. There results VLSI circuits having increased density and reliability.

Abstract: A process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. The method for forming integrated circuits with this structure includes forming openings in a first polycrystalline silicon layer overlying an insulator by reactive ion etching which results in the structure having substantially horizontal surfaces and substantially vertical surfaces. The openings are in those areas designated to be the gate regions of the field effect transistors. A second insulating layer is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the major surface of the silicon body. The gate dielectric is formed hereat.