Abstract: A method and apparatus for testing the proper operation of the optical elements in the optical detection circuit of an electronic register in an energy meter. The light emitter circuit is periodically pulsed adequate to turn the emitters to the on condition, and a comparison circuit is provided in which the voltage across a monitor point in circuit with the light emitters and a switching circuit is monitored both before and after each pulse. The absence of a voltage change upon pulsing the light emitter circuitry is used to generate a first error or failure signal. The light detector is read prior to each pulse to determine if unprogrammed light is being received prior to the pulsing of the light emitter as an indication of tampering with the accurate reading of the energy meter, and a second error signal is generated in response to unprogrammed light.

Abstract: An electronic watthour meter is digitally configurable to operate as several different types of watthour meters for metering electrical energy from a variety of different electric utility services. Automatic scaling of line input currents is provided to scale the voltage input to an analog to digital converter over selected ranges such that low level and high level input signals are measured in an optimum range. A digital signal processor is employed to calculate values for metered electrical energy and output pulses, each proportional to a quantum of energy flowing in the circuit being metered. The processor calculates the value of DC offset errors inherent in the various analog circuits of the meter and uses that value in the calculation of metered electrical energy to compensate for such offset errors. The meter employs automatic and manually initiated test functions for testing the operation of the processor and other critical circuits in the meter.

Abstract: Individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points on one side of the test surface. The probe points electrically contact the contacts on the wafer under test by fluid pressure.

Abstract: A switch probe, generally for use in testing cable harnesses, is for placement within a standard probe receptacle and can be removed and replaced as necessary. The switch probe includes a conductive barrel with a front open end and a rear closed end. A conductive first switch portion is received within the barrel at the rear closed end and includes a first shaft projecting forwardly. A conductive second switch portion is received within the barrel and has an engagement tip positioned forwardly of the barrel open end for electrical contact with a test site. A second shaft extends rearwardly and into axially spaced relation to the first shaft. An elongate hollow insulator extends fully between and provides a guideway for reciprocatory contact between the first and second shafts and fully shields the second shaft from electrical leakage prior to conductive contact of the second shaft with the first shaft.

Abstract: An AC/DC current detection method that can detect small and large changes in current, by employing a high-frequency excitation current applied to a coil wrapped around an annular iron core. The change in this value is determined for operation in the region of the coercive force of the iron core or as the change in an extreme value thereof.

Abstract: Apparatus for testing for defects in the form of ohmic leakage in an antifuse element disposed between first and second conductors in an integrated circuit prior to formation of electronic circuits by a user, includes circuitry, responsive to signals provided to the integrated circuit from an external source, for temporarily connecting together a first group of the conductors to form a circuit path to the first conductor during a first time period. Circuitry, responsive to signals provided to the integrated circuit from an external source, is provided to temporarily connect together a second group of the conductors to form a circuit path to the second conductor during the first time period. Circuitry is provided to place an electrical charge onto the first conductor during a second time period within the first time period such that a selected dynamic first voltage potential is placed on the first conductor.

Abstract: In the present invention a method of testing a partially completely assembled module with integrated circuit dies mounted thereon is disclosed. The partially-completely assembled module has one or more first locations with integrated circuit dies mounted thereon and one or more second locations with integrated circuit dies to be mounted thereon and one or more electrical paths electrically connecting the first and second locations. A supplementary module with one or more electrical components assembled in the second locations and with one or more electrical components to be assembled in the first locations and with electrically identical electrical paths connecting the first and second locations as the testing module is also provided. The testing module and the supplementary module are mated together by electrically connecting the first and second locations of the testing module to the first and second locations of the supplementary module, respectively.

Abstract: A modular ATE system includes a plurality of test modules and a receiver for use with a variety of fixtures to which printed circuit boards are to be coupled. Each test module includes a plurality of pin cards controlled by a single module controller. Multiple test module are included for testing a variety of functions. Test signals are generated by discrete sets of pin cards and controllers, then output to the receiver for interconnection to a fixture and printed circuit board(s) under test. A substantially wireless receiver is provided, including a translation board for electrically coupling test module pin cards to the fixture. By eliminating wiring and cabling by using a prefabricated translation board, noise is substantially reduced and test signal quality improved. The translation board defines prescribed signal mapping for interconnecting the I/O pins of ATE pin cards to the underside of the fixture. Different translation boards may have different mappings.

Abstract: Internal test sites on integrated circuit chips may be tested with minimal input/output pad or chip area overhead by providing transient interconnections to the internal test sites using an optically activated photoconductive layer which is formed over the active device layers of the integrated circuit to be tested. The photoconductive layer may be optically activated using an optical mask or hologram, to electrically access the desired internal test sites. Different test sites may be tested using different masks or holograms. The photoconductive layer is preferably hydrogenated amorphous silicon which is highly compatible with standard integrated circuit processing.

Abstract: The present invention concerns a circuit processes the power signal emitted from an RF power sensor (SK) of a radio telephone to create a detector voltage which is proportional to the power level of the radio telephone transmitter. The circuit comprises a transistor (Q2) acting as an active rectifier, which in the ascending part of the positive half cycle of the power signal charges a capacitor (C3). During the descending part of the power signal the capacitor starts to discharge with a time constant which is remarkably greater than the cycle length of the power signal. The transistor is biassed by means of a transistor (Q1) so that it is conductive even at the lowest power levels.

Abstract: A test apparatus for testing electronic integrated circuitry, a test probe assembly for use in the apparatus, and a method of forming the test probe assembly are provided. The test apparatus subjects electronic integrated circuitry under test to changing temperatures while communicating test signals from external test equipment to the circuitry under test and back to the test equipment. The test probe assembly used in the apparatus is adapted to expand and contract along with the electronic integrated circuitry as the probe assembly and the integrated circuitry are heated and subsequently allowed to cool during testing, thereby maintaining precise alignment of probes on the probe assembly with test contact points on the electronic integrated circuitry.

Abstract: A surface is probed with a pulsed electron beam and secondary electrons are detected to produce a detector signal. First portions of the detector signal are substantially dependent on the voltage of the surface being probed, while second portions of the detector signal are substantially independent of the voltage of the surface being probed. In general, the first and second portions of the detector signal include unwanted noise caused by low-level sampling due to beam leakage and/or by scintillator afterglow in the secondary-electron detector. The detector signal is sampled during the first signal portions and is sampled during the second signal portions. The sampled first signal portions are combined with the complement of the sampled second signal portions to produce a measured voltage signal representing voltage of the conductor. In a preferred sampling scheme, alternate electron-beam sampling pulses are held-off.

Abstract: Apparatus for performing high voltage testing of high-voltage transistors in the programming paths of a user-configurable integrated circuit including a plurality of conductors which may be connected to one another and to functional circuit blocks by programming user-programmable antifuse elements connected thereto to form electronic circuits, prior to formation of the electronic circuits by a user, including circuitry, responsive to signals provided to the integrated circuit from an external source, for temporarily connecting together a first group of the conductors to form a circuit path, the circuit path including the source and drain of at least one of the high-voltage transistors during a selected time period; circuitry for driving the circuit path and the gate of the at least one high-voltage transistor to a first voltage potential during the selected time period; circuitry for driving the bulk semiconductor region in the integrated circuit containing the source and drain of the at least one high-voltag

Abstract: An apparatus and method for testing an integrated circuit (12) generally comprises an input pad (14) and output pad (15) having photo-sensitive sensors (20, 46) formed thereon for eliminating the need to come into direct contact with a probe card for testing the integrity of an integrated circuit.

Abstract: A contact assembly for use in testing electric devices such as integrated circuits (IC's) and the like is comprised of a test socket and a corresponding carrier module for positioning the electric devices to be tested in alignment with the test socket. The carrier module is provided with a holding mechanism for retaining electronic devices to be tested in their proper position in the seat of the module, the holding mechanism being retractable so as to not interfere with the electrical contact between the socket and the electric device. In another aspect of the present invention, the contact assembly is provided with a slide positioning mechanism for slidably positioning the electronic device in its proper location on the seat of the carrier module.

Abstract: On-chip circuitry facilitates fuse testing in customized integrated circuits. The circuitry has specific application in testing fuse redundancy high end memories. A latch assisted fuse testing (LAFT) methodology employs an on-chip latch stack which can be used in place of the fuses. The latches in the stack are programmable and can perform the same function as the fuses during chip operation. This allows testing or experimentation to be performed nondestructively, without blowing any fuses. In one particular application of the invention, memory arrays with redundant blocks on a chip are provided with the on-chip latch stack. After the tests based on previously generated error data are performed using the latch stack, fuses are blown to repair the memory array by replacing defective memory blocks with redundant blocks.

Abstract: A microwave power sensor is disclosed which is capable of using diodes above their resonant frequency to sense the power of input microwaves. The power sensor includes a sensing diode, a conditioning means, and a tapered waveguide. For input waves having frequencies near and above the resonant frequency of the sensing diode, the output of the diode begins to be frequency dependent. That is, the diode outputs different DC signals for waves having different frequencies even though the power of the waves is the same. The conditioning apparatus is adapted to offset the frequency dependence of the diode by varying the fraction of the input wave that is transmitted to the diode so as to cause the output of the diode to be relatively constant for waves having equal power but different frequencies. The conditioning apparatus also provides a load impedance which matches the characteristic impedance of the input wave to minimize the reflection of the input wave.

Abstract: A head assembly for a vacuum actuated printed circuit board test fixture includes a top plate adapted for receiving a printed circuit board thereon, a probe plate having a plurality of spring-loaded contact probes thereon, and a support assembly for supporting the top plate in sealed relation above the probe plate. The support assembly includes a primary seal member having a channel formed therein and a resilient secondary seal member in the channel which cooperates with the primary seal member to provide a seal between the top plate and the probe plate around the entire perimeter of the top plate and to support the top plate so that it is movable toward the probe plate by resiliently compressing the secondary seal member.

Abstract: A method and apparatus for determining the carrier concentration and profile depth for pn semiconductor structures, and band discontinuities for heterojunction pn structures is disclosed. A more accurate measurement of carrier concentration and profile depth is obtained by initially measuring the pn junction intercept voltage of a pn semiconductor structure to be tested before the structure is exposed to a conventional capacitance-voltage (C-V) profiling process. The pn junction intercept voltage is employed to determine the pn junction capacitance which can then be compensated for in capacitance dependent formulae used for calculating the carrier concentration and profile depth. The intercept voltage can also be used to determine band discontinuities in a heterojunction pn structure. A fixed or retractable metal contact is employed to contact the p-type layer of a pn semiconductor structure to be tested and permit this initial measurement to be obtained.

Abstract: A probe apparatus has a quartz probe formed of a quartz probe body and a metallic pattern layer formed thereon, the quartz probe body including a plurality of probe portions having a large number of probes corresponding to an electrode array of an object of examination, lead pattern portions continuous individually with the probe portions, and a supporting portion supporting all the lead pattern portions, the quartz probe body being designed so that the longitudinal direction of each probe is inclined with respect to a crystal axis X or Y of a quartz plate by etching a Z plane of the quartz plate perpendicular to a crystal axis Z of the quartz plate, and a tester fitted with the quartz probe by means of an adapter.