Abstract: Chip performance is measured using LSSD logic to propagate a signal through the LSSD scan path of the chip. The measurement data is compared to tabular data which is used to classify the AC chip performance. The use of the LSSD scan path provides an accurate overall measurement of an entire chip. The circuitry is internal to the system and does not require external test circuitry. No unique test patterns are required for a given chip design. The chip measurements can be made after installation of the chip in a field operational environment as well as during a manufacturing and testing environment. The chip measurements can be made by local execution of the testing or controlled from a remote location.

Abstract: A voltage rotation indicator for testing the phase sequence of live multi-phase electrical power is mounted within a housing. The housing is provided with structure for removably mounting the indicator on a meter box or can during voltage rotation testing. Contact plungers extend from the housing and contact meter jaw test points in the meter box during testing. Field personnel are thus not required to insert their hands into the meter box to attach test clips to the live circuit.

Abstract: A plural test mode selection circuit in a semiconductor device capable of extending the number of option modes, e.g., up to 16 option modes by adding a high voltage sensing circuit 15 to any one of a plurality of input pads and by arranging a master decoder 25 and a slave decoder 20 each coupled to a plurality of buffer circuits 11-14, as well as a mode selector 30 and a plurality of address/control pads 5-9, and then an output of a high voltage sensing circuit 15 and respective outputs of the master decoder 25 and a slave decoder 20 are combined together at a mode selector 30, so that a plurality of test modes selection is possible therefrom. In addition, the invention also has an advantage capable of testing a chip even after it has been made into a package because of utilizing the address/control pad used in a general read/write operation.

Abstract: A circuit arrangement for detecting an input voltage comprises an oscillator responsive to the voltage, the oscillator including a pair of transistors (8, 9) connected as an astable multivibrator, each of the transistors having a load which comprises a primary winding (16 or 17) of a current transformer (T) and a low resistance proof resistor (12 or 13). A current flows through a secondary winding (18) of the transformer the amplitude of which current is proportional to the input voltage.

Abstract: A digital level display device wherein the digital input signal is converted into an absolute value and further converted into its logarithm. The peak of the logarithm is detected and latched. A CPU reads the latched peak and converts into it into a signal for display.

Abstract: Disclosed is a method of measuring physical properties of a buried channel, e.g., a generation current in a semiconductor substrate in which the buried channel is formed, a generation current of the surface of the semiconductor substrate, a channel potential and a surface potential of the buried channel. A gate ramp voltage is applied to a gate electrode formed over the buried channel and a current generated from a depletion layer at the buried channel and a gate current produced by changes in the capacitance of the buried channel are measured. The physical properties of the buried channel are obtained from the measured currents.

Abstract: The present invention provides a circuit board tester for performing functional and in-circuit tests on one or more circuit boards. The circuit board tester includes a testhead for interfacing with one or more circuit boards and supplying the resources for the testing thereof. The testhead includes a plurality of modules with each module having a defined amount of resources and a processor for use in executing a test plan to test the circuit board. The circuit board tester further includes a high-speed link for coordinating the execution of a test plan by two or more modules when the resources of one module are insufficient to test a particular circuit board. Each module in the testhead can be selectively connected or disconnected from the high-speed link. Consequently, two or more modules can be connected to the high-speed link to test a first circuit board while another module, that is disconnected from the high-speed link, can concurrently test a second circuit board.

Abstract: A method and an apparatus for measuring and testing an electric characteristic of a semiconductor device in a non-contact fashion by using an electron beam to induce a voltage on the semiconductor device. By examination of changes with a lapse of time of the induced voltage, the electric characteristics of the semiconductor device are determined.

Abstract: A system for testing integrated circuits is disclosed which uses a mechanical microprobe and the integrated circuit's CAD database. The system is integrated with the CAD database in such a manner that after an initial alignment operation between the CAD database and the integrated circuit being tested, the microprobe can be moved automatically to any spot on the circuit by choosing a point in the CAD database and placing a cursor on that spot. The microprobe is then automatically moved to the point so indicated. A contact sensing circuit allows the probe to be driven into the actual circuit to take measurements or inject test signals without fear of damaging the integrated circuit. The system can operate in numerous modes, each of which provide a different way of visualizing the circuit being tested.

Abstract: An electronic component test procedure which can employ a combination of stress, test, and sort techniques useful for consolidating package test, burn-in test and qualification tests. The process can be automated to avoid batch process and virtually eliminate manual handling. Components are sorted according to initial values and mathematical stress models.

Abstract: A device testing system of the type in which an electronic test head is mounted for pivotal movement about three orthogonal axes. Cables are connected between a test cabinet and the test head to carry electronic signals. The test head is directly mounted to, and the cable is introduced to the test head through, a split ring cable pivot.

Abstract: The device of the invention comprises a main optical sensor (3) suitable for measuring a changing physical parameter, and a secondary optical sensor (6) suitable for measuring a disturbance which influences the measurement of said physical parameter, but for which the frequency spectrum is disjoint from that of the parameter. The sensors (3) and (6) are connected in series such that the main sensor serves to modulate the beam received by the secondary sensor.

Abstract: The measuring device of the rms value of a signal comprises, in series, a full-wave rectifier, a low-pass filter, for example of the RC type, and a peak detector. The output signal of the device is representative of the rms value of the input signal, the cut-off frequency of the filter corresponding to an angular frequency comprised between 4.pi.f/6 and 4.pi.f/5.33, f being the fundamental frequency of the input signal of the device.

Abstract: A burn-in apparatus includes burn-in boards for holding semiconductor devices through air suction and for electrically connecting them to external equipment. Since the semiconductor devices are held on the burn-in boards for electrical connection through air suction, sockets are not necessary to hold them on the boards which reduces costs. Further, the leads of semiconductor devices, which have conventionally been susceptible to bending when inserted into or extracted from the sockets, can be protected.

Abstract: A test selection system is provided which includes a semiconductor substrate having a pin connected thereto and an integrated circuit disposed on the substrate and connected to the pin having an operating voltage within a given voltage range. A latch conditioning circuit having an input responsive to a voltage of a given magnitude has an output connected to a latch, and a voltage control circuit operable at a voltage without the given voltage range selectively applies a control voltage of the given magnitude to the input of the latch conditioning circuit. A voltage without the given voltage range is applied to the pin during a first interval of time to produce the control voltage for establishing a test mode and a voltage within the given voltage range is applied to the pin during a second interval of time to establish a normal operating mode for the integrated circuit.

Abstract: An electronic watthour meter for metering the consumption of electrical energy on power lines includes phase compensation means for compensating for leading and lagging phase differences between line current and voltage, whereby sampling times of the current and voltage are shifted to compensate for phase errors between the current and voltage by controlling timing signals provided to current and voltage analog to digital converters. Digital output signals from the analog to digital converters proportional to current and voltage are multiplied to provide an accurate representation of energy consumption as a result of the compensation.

Abstract: A microwave calorimeter is disclosed for substantially measuring the total icrowave energy in an applied microwave pulse. The microwave calorimeter includes: a housing having a highly reflective interior surface, a microwave absorbing device disposed in the housing for substantially absorbing microwave energy transmitted into the housing and for producing a thermal response proportional to the amount of microwave energy being absorbed, and a measurement device responsive to the thermal response for determining the amount of microwave energy being absorbed by the microwave absorbing device.

Abstract: A high density probe for probing an integrated circuit package in situ on a circuit board has a probe body with a skirt that has alignment surfaces for mating with the package to provide an initial alignment. An alignment plate is elastically mounted within the probe housing internal of the skirt. The alignment plate has serrations between pin holes, the pin holes corresponding to probe pins elastically mounted on the probe housing in a pattern matching the leads of the integrated circuit package. When the probe is pressed down over the integrated circuit package the alignment surfaces within the skirt align the probe to the package, and the serrations mesh with the leads to align the probe pins with the leads, the probe pins extending through the pin holes and maintaining positive contact due to the elastic mounting of the pins.

Abstract: Relays and toggle switches for programming the electrical interconnections between automated test equipment and the pins of a DUT are replaced with manually programmable jumpers connected between various jumper terminals mounted on a jumper programmable interface board. The jumper terminals are located on the interface board in close proximity to the pins of a DUT to minimize interference and crosstalk. Pulldown and pullup resistors as well as bypass capacitors are optionally incorporated into the jumpers. The jumper terminals provide easy access to pin electronics (PE) test signals and to various power and ground plane in a multilayer interface board so that the test conditions for each pin can be manually programmed by selection of jumper connections.

Abstract: A method of testing unpackaged integrated circuits using a tester which is capable of testing a plurality of memories in parallel is provided. A membrane test head having a plurality of probe bumps thereon is provided wherein the probe bumps are coupled to the tester by microstrip transmission lines formed on the membrane test head. The semiconductor memory has a plurality of contact pads thereon which are coupled to the probes. In this manner, a plurality of semiconductor memories can be tested in wafer form. Alternatively, individual semiconductor memory chips can be mounted on a receiver plate and tested individually or in parallel by moving the receiver plate so that the contact pads couple to the probes.