Patents Examined by William M. Treat
  • Patent number: 8082429
    Abstract: An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor; a data processing unit that performs particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue an interrupt request to execute an exception handler to the processor.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: December 20, 2011
    Assignee: Panasonic Corporation
    Inventors: Hideshi Nishida, Takeshi Furuta, Tetsuya Tanaka, Kozo Kimura, Tokuzo Kiyohara
  • Patent number: 8078834
    Abstract: A digital signal processor includes a control block configured to issue instructions based on a stored program, and a compute array including two or more compute engines configured such that each of the issued instructions executes in successive compute engines of at least a subset of the compute engines at successive times. The digital signal processor may be utilized with a control processor or as a stand-alone processor. The compute array may be configured such that each of the issued instructions flows through successive compute engines of at least a subset of the compute engines at successive times.
    Type: Grant
    Filed: January 9, 2008
    Date of Patent: December 13, 2011
    Assignee: Analog Devices, Inc.
    Inventor: Douglas Garde
  • Patent number: 8055883
    Abstract: A data processing apparatus 1 has a plurality of registers 10 of the same type of register and a plurality of processing pipelines 40, 50, each processing pipeline 40, 50 being arranged to process instructions. At least one instruction includes a destination register specifier specifying which of said registers is a destination register for storing a processing result of the at least one instruction. Instruction issuing circuitry 26 is configured to issue the at least one instruction for processing by one of the plurality of processing pipelines. The instruction issuing circuitry 26 selects the one of the plurality of processing pipelines to which the candidate instruction is issued in dependence upon the value of the destination register specifier of the candidate instruction.
    Type: Grant
    Filed: July 1, 2009
    Date of Patent: November 8, 2011
    Assignee: ARM Limited
    Inventor: David Raymond Lutz
  • Patent number: 8037286
    Abstract: The present invention provides a data processing apparatus comprising processing circuitry for executing a sequence of instructions and pre-decoding circuitry for receiving the instructions fetched from memory. The pre-decoding circuitry performs a pre-decoding operation to generate corresponding pre-decoded instructions and stores them in a cache for access by the processing circuitry. For each instruction fetched from the memory, the pre-decoding circuitry detects whether the instruction is an abnormal instruction and upon such detection provides in association with a corresponding pre-decoded instruction an identifier identifying that instruction as abnormal.
    Type: Grant
    Filed: January 23, 2008
    Date of Patent: October 11, 2011
    Assignee: ARM Limited
    Inventor: Peter Richard Greenhalgh
  • Patent number: 7996618
    Abstract: A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.
    Type: Grant
    Filed: January 28, 2011
    Date of Patent: August 9, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F Robinson, Sumedh W Sathaye, Jeffrey R Summers
  • Patent number: 7987340
    Abstract: Data is transmitted from a sending processor over a network to one or more receiving processor in a forward direction during an allocated slot, and acknowledge signals are sent in a reverse direction during the same allocated slot, to indicate whether the receiving processor is able to receive data If one or more of the receiving processors indicates that it is unable to receive the data, the data is retransmitted during the next allocated slot. This means that the sending processor is able to determine within the slot period whether a retransmission is necessary, but that the slot period only needs to be long enough for one-way communication.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: July 26, 2011
    Inventors: Gajinder Panesar, Anthony Peter John Claydon, William Philip Robbins, Alex Orr, Andrew Duller
  • Patent number: 7984275
    Abstract: In a logically partitioned host computer system comprising host processors (host CPUs), a facility and instruction for discovering topology of one or more guest processors (guest CPUs) of a guest configuration comprises a guest processor of the guest configuration fetching and executing a STORE SYSTEM INFORMATION instruction that obtains topology information of the computer configuration. The topology information comprising nesting information of processors of the configuration and the degree of dedication a host processor provides to a corresponding guest processor. The information is preferably stored in a single table in memory.
    Type: Grant
    Filed: May 13, 2010
    Date of Patent: July 19, 2011
    Assignee: International Business Machiness Corporation
    Inventors: Mark S. Farrell, Charles W. Gainey, Jr., Jeffrey P. Kubala, Donald W. Schmidt
  • Patent number: 7979678
    Abstract: A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A tag is assigned to each instruction in the variable advance instruction window. The tag of each instruction to leave the window is assigned to the next new instruction to be added to it. The results of instructions executed by the processor are stored in a temp buffer according to their corresponding tags to avoid output and anti-dependencies. The temp buffer therefore permits the processor to execute instructions out of order and in parallel. Data dependency checks for input dependencies are performed only for each new instruction added to the variable advance instruction window and register renaming is performed to avoid input dependencies.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: July 12, 2011
    Assignee: Seiko Epson Corporation
    Inventors: Trevor A. Deosaran, Sanjiv Garg, Kevin R. Iadonato
  • Patent number: 7979673
    Abstract: A processor is adapted for performing a QR-decomposition. The processor has a program memory, a program controller, connected to the program memory to receive program instructions, and at least one processing unit. The processing unit includes a CORDIC calculation block, and has a distributed memory structure, with separate memory blocks for storing respective parameter values.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: July 12, 2011
    Assignee: Altera Corporation
    Inventor: Michael Fitton
  • Patent number: 7979675
    Abstract: A microprocessor includes a register that stores a state and a fetch unit that fetches instructions of a program. The program includes a first instruction followed non-immediately by a second instruction. The first instruction instructs the microprocessor to update the state in the register. The second instruction is a conditional branch instruction that specifies a branch condition based on the register state. The fetch unit dispatches the first instruction for execution but refrains from dispatching the second instruction for execution. Execution units receive the first instruction from the fetch unit and responsively update the register state. The fetch unit non-selectively correctly resolves the conditional branch instruction based on the register state when the execution units have updated the register state.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: July 12, 2011
    Assignee: VIA Technologies, Inc.
    Inventors: G. Glenn Henry, Terry Parks, Brent Bean
  • Patent number: 7975132
    Abstract: A microprocessor having a plurality of call/return stacks (CRS) correctly resolves a call or return instruction rather than issuing the instruction to execution units of the microprocessor to be resolved. The microprocessor fetches a call or return instruction and determines whether the instruction is the first call or return instruction fetched after fetching a conditional branch instruction that has yet to be resolved. The microprocessor copies the contents of a current CRS to another CRS and designates the other CRS as the current CRS, if the state exists. The microprocessor pushes the address of the next sequential instruction following the call instruction onto the current CRS and fetches an instruction at the call instruction target address if the instruction is a call instruction. The microprocessor pops a second return address from the current CRS and fetches an instruction at the second return address, if the instruction is a return instruction.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: July 5, 2011
    Assignee: VIA Technologies, Inc.
    Inventors: Brent Bean, Terry Parks, G. Glenn Henry
  • Patent number: 7966475
    Abstract: A data processor comprises a plurality of processing elements arranged for parallel processing of data, and a controller for controlling the plurality of processing elements. The controller is operable to determine respective status information for a plurality of processing threads, and to control processing of the processing threads by the plurality of processors in dependence upon such status information.
    Type: Grant
    Filed: January 10, 2007
    Date of Patent: June 21, 2011
    Assignee: Rambus Inc.
    Inventors: Dave Stuttard, Dave Williams, Eamon O'Dea, Gordon Faulds, John Rhoades, Ken Cameron, Phil Atkin, Paul Winser, Russell David, Ray McConnell, Tim Day, Trey Greer
  • Patent number: 7958332
    Abstract: A controller operable to control an array of processing elements comprises a retrieval unit operable to retrieve instruction items for each of a plurality of instructions streams, each instruction stream having a plurality of instructions items, a combining unit operable to combine the plurality of instruction streams into a serial instruction stream, and a distribution unit operable to distribute the serial instruction stream to an array of processing elements.
    Type: Grant
    Filed: March 13, 2009
    Date of Patent: June 7, 2011
    Assignee: Rambus Inc.
    Inventors: Dave Stuttard, Dave Williams, Eamon O'Dea, Gordon Faulds, John Rhoades, Ken Cameron, Phil Atkin, Paul Winser, Russell David, Ray McConnell, Tim Day, Trey Greer
  • Patent number: 7937566
    Abstract: A processing bypass directory system and method are disclosed. In one embodiment, a bypass directory tracking process includes setting bits in a bypass directory when a corresponding architectural register is written. The configuration of the bits is utilized to determine which stage of a bypass path processing information is at.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: May 3, 2011
    Inventors: Alexander Klaiber, Guillermo Rozas
  • Patent number: 7934082
    Abstract: An information processing apparatus performs switching between an exception handler and normal processing. The information processing apparatus includes a processor a data processing unit that performs a particular processing upon receiving a processing request from the processor; an interrupt controller that issues an interrupt request to the processor; and an exception control unit that controls the interrupt controller, wherein the data processing unit is connected with the exception control unit via a dedicated line. The data processing unit includes a notification unit that notifies, via the dedicated line, the exception control unit of status information indicating current status of the data processing unit, and based on the notified status information and setup information set by the processor, the exception control unit judges whether to cause the interrupt controller to issue to the processor an interrupt request to execute an exception handler.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: April 26, 2011
    Assignee: Panasonic Corporation
    Inventors: Hideshi Nishida, Takeshi Furuta, Tetsuya Tanaka, Kozo Kimura, Tokuzo Kiyohara
  • Patent number: 7934081
    Abstract: A single unified level one instruction(s) cache in which some lines may contain traces and other lines in the same congruence class may contain blocks of instruction(s) consistent with conventional cache lines. Formation of trace lines in the cache is delayed on initial operation of the system to assure quality of the trace lines stored.
    Type: Grant
    Filed: October 5, 2006
    Date of Patent: April 26, 2011
    Assignee: International Business Machines Corporation
    Inventors: Gordon T. Davis, Richard W. Doing, John D. Jabusch, M V V Anil Krishna, Brett Olsson, Eric F. Robinson, Sumedh W. Sathaye, Jeffrey R. Summers
  • Patent number: 7930686
    Abstract: A handle for a trace is provided that is memory indifferent. The handle is created using contents of the trace rather than memory location of the trace. This enables the trace to be easily identified in subsequent runs of an application associated with the trace.
    Type: Grant
    Filed: June 19, 2009
    Date of Patent: April 19, 2011
    Assignee: International Business Machines Corporation
    Inventors: Marcel Mitran, Ali L. Sheikh
  • Patent number: 7925867
    Abstract: A data processing and method are provided for pre-decoding instructions. The data processing apparatus has pre-decoding circuitry for receiving instructions fetched from a memory and for performing a pre-decoding operation to generate corresponding pre-decoded instructions, which are then stored in the cache for access by the processing circuitry. If a pre-decoded instruction crosses a cache line boundary, then checking circuitry in respect of selected types of pre-decoded instruction checks for consistency between the first portion of the pre-decoded instruction stored within a first cache line and a contiguous second portion of the pre-decoded instruction stored within a second cache line. If this consistency check is passed such that the two portions are self-consistent, then the pre-decoded instruction can be further decoded and issued.
    Type: Grant
    Filed: July 14, 2009
    Date of Patent: April 12, 2011
    Assignee: ARM Limited
    Inventors: Peter Richard Greenhalgh, Max Zardini, Allan John Skillman, Daniel Paul Schostak
  • Patent number: 7925866
    Abstract: A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-decoding circuitry receives the instructions fetched from the memory and performs a pre-decoding operation to generate corresponding pre-decoded instructions, with those pre-decoded instructions then being stored in a cache for access by the processing circuitry. The pre-decoding circuitry performs the pre-decoding operation assuming a speculative processor state, and the cache is arranged to store an indication of the speculative processor state in association with the pre-decoded instructions.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: April 12, 2011
    Assignee: ARM Limited
    Inventors: Peter Richard Greenhalgh, Andrew Christopher Rose, Simon John Craske, Max Zardini
  • Patent number: RE42466
    Abstract: A branch history stores execution history information of branch instructions, and predicts presence of a branch instruction and a corresponding branch destination. A first return address stack stores, when an execution of a call instruction of a subroutine is completed, address information of a return destination of a corresponding return instruction. A second return address stack stores, when presence of a call instruction of a subroutine is predicted, address information of a return destination of a corresponding return instruction. An output selecting unit selects, when presence of a return instruction is predicted, if address information is stored in the second return address stack, the address information as a result of the branch prediction with a highest priority, and outputs the address information selected.
    Type: Grant
    Filed: January 15, 2010
    Date of Patent: June 14, 2011
    Assignee: Fujitsu Limited
    Inventor: Megumi Yokoi