Patents Examined by William M. Treat
  • Patent number: 7647518
    Abstract: In one embodiment, a processor comprises a scheduler configured to issue a first instruction operation to be executed and an execution core coupled to the scheduler. Configured to execute the first instruction operation, the execution core comprises a plurality of replay sources configured to cause a replay of the first instruction operation responsive to detecting at least one of a plurality of replay cases. The scheduler is configured to inhibit issuance of the first instruction operation subsequent to the replay for a subset of the plurality of replay cases. The scheduler is coupled to receive an acknowledgement indication corresponding to each of the plurality of replay cases in the subset, and is configured to inhibit issuance of the first instruction operation until the acknowledge indication is asserted that corresponds to an identified replay case of the subset.
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: January 12, 2010
    Assignee: Apple Inc.
    Inventors: Po-Yung Chang, Wei-Han Lien, Jesse Pan, Ramesh Gunna, Tse-Yu Yeh, James B. Keller
  • Patent number: 7627743
    Abstract: A multi-word transfer instruction, a memory transfer method using the multi-word transfer instruction and a circuit implementation for transferring multiple words between a memory subsystem and a processor register file are provided. The multi-word transfer instruction specifies an access type (load or store), a consecutive register group, a selection mask and a base register for the starting address of the corresponding memory locations. Therefore, the total number of words accessed by this instruction is equal to the number of registers specified in the consecutive register group along with the number of the registers specified by the selection mask. Besides, additional information, such as an address update mode, an order mode and a modification mode, may be further specified in the multi-word transfer instruction.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: December 1, 2009
    Assignee: Andes Technology Corporation
    Inventors: Hong-Men Su, Chuan-Hua Chang, Jen-Chih Tseng
  • Patent number: 7624254
    Abstract: A processor pipeline is segmented into an upper portion—prior to instructions going out of program order—and one or more lower portions beyond the upper portion. The upper pipeline is flushed upon detecting that a branch instruction was mispredicted, minimizing the delay in fetching of instructions from the correct branch target address. The lower pipelines may continue execution until the mispredicted branch instruction confirms, at which time all uncommitted instructions are flushed from the lower pipelines. Existing exception pipeline flushing mechanisms may be utilized, by adding a mispredicted branch identifier, reducing the complexity and hardware cost of flushing the lower pipelines.
    Type: Grant
    Filed: January 24, 2007
    Date of Patent: November 24, 2009
    Assignee: QUALCOMM Incorporated
    Inventors: Rodney Wayne Smith, James Norris Dieffenderfer, Michael Scott McIlvaine, Thomas Andrew Sartorius
  • Patent number: 7620798
    Abstract: A synchronization mechanism is used to synchronize events across multiple execution pipelines that process transaction streams. A common set of state configuration is included in each transaction stream to control processing of data that is distributed between the different transaction streams. Portions of the state configuration correspond to portions of the data. Execution of the transaction streams is synchronized to ensure that each portion of the data is processed using the state configuration that corresponds to that portion of the data. The synchronization mechanism may be used for multiple synchronizations and when the synchronization signals are pipelined to meet chip-level timing requirements.
    Type: Grant
    Filed: October 30, 2006
    Date of Patent: November 17, 2009
    Assignee: NVIDIA Corporation
    Inventors: Mark J. French, Steven E. Molnar
  • Patent number: 7620796
    Abstract: A system and method for accelerated processing of streams of dependent instructions, such as those encountered in the G.726 codec, in a microprocessor or microprocessor-based system/chip. In a preferred implementation, a small RISC-like special purpose processor is implemented within a larger general purpose processor for handling the streams of dependent instructions.
    Type: Grant
    Filed: January 16, 2007
    Date of Patent: November 17, 2009
    Assignee: Broadcom Corporation
    Inventors: Sophie M. Wilson, Alexander J. Burr
  • Patent number: 7617493
    Abstract: A handle for a trace is provided that is memory indifferent. The handle is created using contents of the trace rather than memory location of the trace. This enables the trace to be easily identified in subsequent runs of an application associated with the trace.
    Type: Grant
    Filed: January 23, 2007
    Date of Patent: November 10, 2009
    Assignee: International Business Machines Corporation
    Inventors: Marcel Mitran, Ali I. Sheikh
  • Patent number: 7610475
    Abstract: A processing system with reconfigurable instruction extensions includes a processor, programmable logic, a register file, and a load/store module. The processor executes a computer program comprising a set of computational instructions and at least one instruction extension. The programmable logic receives configuration information to configure the programmable logic for the instruction extension and executes the instruction extension. The register file is coupled to the programmable logic and stores data. The load/store module transfers the data directly between the register file and a system memory.
    Type: Grant
    Filed: August 15, 2005
    Date of Patent: October 27, 2009
    Assignee: Stretch, Inc.
    Inventors: Jeffrey Mark Arnold, Gareld Howard Banta, Scott Daniel Johnson, Albert R. Wang
  • Patent number: 7606996
    Abstract: An array calculation device that includes a processor array composed of a plurality of processor elements having been assigned with orders, acquires an instruction in each cycle, generates, in each cycle, operation control information for controlling an operation of a processor element of a first order, and then generates an instruction to the processor element of the first order in accordance with the operation control information and the acquired instruction, and also generates, in each cycle, operation control information for controlling an operation of each processor element of a next order and onwards, in accordance with operation control information generated for controlling an operation of a processor element of an immediately preceding order, and then generates an instruction to each processor element of the next order and onwards, in accordance with the operation control information generated and the acquired instruction.
    Type: Grant
    Filed: August 2, 2005
    Date of Patent: October 20, 2009
    Assignee: Panasonic Corporation
    Inventors: Hiroyuki Morishita, Takeshi Tanaka, Masaki Maeda, Yorihiko Wakayama
  • Patent number: 7596781
    Abstract: A register-based instruction optimization is provided for facilitating efficient emulation of a target instruction stream. The optimization includes for at least one instruction in a frequently executed sequence of target instructions: confirming that at least one register is marked as a read-only register for the sequence; confirming that each register of the at least one register has been detected to have a constant value for the at least one instruction in multiple prior iterations of the executed sequence; and response thereto, optimizing the at least one instruction by replacing the at least one instruction with at least one immediate form instruction having at least one constant value encoded directly therein from the at least one register. The optimization results in an optimized sequence of target instructions, which when translated into a sequence of host instructions, is more efficiently executed by a host computing environment.
    Type: Grant
    Filed: October 16, 2006
    Date of Patent: September 29, 2009
    Assignee: International Business Machines Corporation
    Inventors: Mike S. Fulton, Ali I. Sheikh
  • Patent number: 7594097
    Abstract: A method and apparatus are provided for controlling instructions provided by a microprocessor output port to other execution units. A microprocessor pipeline of instructions is provided for each execution unit. These are scheduled via the microprocessor unit for each execution unit, a determination is made as to whether or not the execution unit can receive further instructions. If it cannot, it's associated pipeline is said to be stalled and instructions are deleted from the microprocessor pipeline. Its thread can then be restarted at a later time with the instruction corresponding to the instruction which was unable to execute.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: September 22, 2009
    Assignee: Imagination Technologies Limited
    Inventor: Andrew Webber
  • Patent number: 7590832
    Abstract: An information processing device for executing a compressed program includes: an instruction buffer; a first selector for selectively outputting one of a set of signals obtained by dividing the output from the instruction buffer; an instruction decompression section for decompressing the output from the first selector into an original instruction; a second selector for outputting the output from the instruction buffer when no compressed instruction is stored in the instruction buffer and outputting the output from the instruction decompression section otherwise; an instruction decoding section for outputting a signal indicating presence/absence of instruction branching based on a result of decoding the output from the selector; and a control section for instructing the first selector to select a predetermined one of the received signals when the signal from the instruction decoding section indicates that there is instruction branching.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: September 15, 2009
    Assignee: Panasonic Corporation
    Inventor: Hiroshi Taniuchi
  • Patent number: 7571300
    Abstract: A memory system includes a plurality of memory blocks, each having a dedicated local arithmetic logic unit (ALU). A data value having a plurality of bytes is stored such that each of the bytes is stored in a corresponding one of the memory blocks. In a read-modify-write operation, each byte of the data value is read from the corresponding memory block, and is provided to the corresponding ALU. Similarly, each byte of a modify data value is provided to a corresponding ALU on a memory data bus. Each ALU combines the read byte with the modify byte to create a write byte. Because the write bytes are all generated locally within the ALUs, long signal delay paths are avoided. Each ALU also generates two possible carry bits in parallel, and then uses the actual received carry bit to select from the two possible carry bits.
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: August 4, 2009
    Assignee: Integrated Device Technologies, Inc.
    Inventor: Tak Kwong Wong
  • Patent number: 7571305
    Abstract: A data processing system 2 includes an instruction cache 6 having an associated buffer memory 18, 8. The buffer memory 18, 8 can operate in a buffer mode or in a microcache mode. The buffer memory is switched into the microcache mode upon program loop detection performed by loop detector circuitry 20. When operating in the microcache mode, instruction data is read from the buffer memory 18, 8 without requiring an access to the instruction cache 6.
    Type: Grant
    Filed: January 11, 2007
    Date of Patent: August 4, 2009
    Assignee: ARM Limited
    Inventors: Fredrick Claude Marie Piry, Louis-Marie Vincent Mouton, Stephane Eric Sabastien Brochier, Gilles Eric Grandou
  • Patent number: 7558945
    Abstract: A system and method for performing register renaming of source registers in a processor having a variable advance instruction window for storing a group of instructions to be executed by the processor, wherein a new instruction is added to the variable advance instruction window when a location becomes available. A tag is assigned to each instruction in the variable advance instruction window. The tag of each instruction to leave the window is assigned to the next new instruction to be added to it. The results of instructions executed by the processor are stored in a temp buffer according to their corresponding tags to avoid output and anti-dependencies. The temp buffer therefore permits the processor to execute instructions out of order and in parallel. Data dependency checks for input dependencies are performed only for each new instruction added to the variable advance instruction window and register renaming is performed to avoid input dependencies.
    Type: Grant
    Filed: September 27, 2005
    Date of Patent: July 7, 2009
    Assignee: Seiko Epson Corporation
    Inventors: Trevor A. Deosaran, Sanjiv Garg, Kevin R. Iadonato
  • Patent number: 7546476
    Abstract: A method is provided for reducing the power consumption of a pipelined microprocessor system arranged to run a program stored in a memory. The method comprises duplicating at least one branch instruction so as to reduce the number of transitions on the bus between the microprocessor and the memory when the program is executed.
    Type: Grant
    Filed: October 9, 2007
    Date of Patent: June 9, 2009
    Assignee: AT&T Corp.
    Inventors: Paul Webster, Phil Endecott, Alan Mycroft
  • Patent number: 7529907
    Abstract: Load and store operations in computer systems are extended to provide for Stream Load and Store and Masked Load and Store. In Stream operations a CPU executes a Stream instruction that indicates by appropriate arguments a first address in memory or a first register in a register file from whence to begin reading data entities, and a first address or register from whence to begin storing the entities, and a number of entities to be read and written. In Masked Load and Masked Store operations stored masks are used to indicate patterns relative to first addresses and registers for loading and storing. Bit-string vector methods are taught for masks.
    Type: Grant
    Filed: October 22, 2007
    Date of Patent: May 5, 2009
    Assignee: MIPS Technologies, Inc.
    Inventors: Mario D. Nemirovsky, Stephen Melvin, Enrique Musoll, Narendra Sankar
  • Patent number: 7526630
    Abstract: A controller operable to control an array of processing elements comprises a retrieval unit operable to retrieve instruction items for each of a plurality of instructions streams, each instruction stream having a plurality of instructions items, a combining unit operable to combine the plurality of instruction streams into a serial instruction stream, and a distribution unit operable to distribute the serial instruction stream to an array of processing elements.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: April 28, 2009
    Assignee: Clearspeed Technology, PLC
    Inventors: Dave Stuttard, Dave Williams, Eamon O'Dea, Gordon Faulds, John Rhoades, Ken Cameron, Phil Atkin, Paul Winser, Russel David, Ray McConnell, Tim Day, Trey Greer
  • Patent number: 7523446
    Abstract: A computer system is provided with memory divided by the operating system into kernel space and user space. A probe function is provided in a related user-space application to support dynamic insertion of instrumentation into the application. A breakpoint instruction is provided in an area of the process's user space that will not be overwritten to support execution of an instrumentation subroutine when a probed subroutine in the application returns.
    Type: Grant
    Filed: November 30, 2006
    Date of Patent: April 21, 2009
    Assignee: International Business Machines Corporation
    Inventor: James A. Keniston
  • Patent number: 7512772
    Abstract: A method for low cost handling of soft error in a microprocessor system is described, which includes detecting a soft error, indicating a register having soft error to an instruction unit, flushing microprocessor pipelines, identifying locations from which to recover a good architectural state based on execution resources used for processing, and recovering the good architectural state from duplicate execution resources used for processing.
    Type: Grant
    Filed: January 8, 2007
    Date of Patent: March 31, 2009
    Assignee: International Business Machines Corporation
    Inventors: Michael Karl Gschwind, Robert Philhower
  • Patent number: RE40693
    Abstract: A method and apparatus for creating virtual worlds wherein a user may begin with a database containing a limited pictorial representation of a desired virtual world and then edit the database to specify the remaining data needed to create the actual virtual world. In one embodiment of the present invention, a database containing a limited pictorial representation of a virtual world is communicated to a receiving unit, and a grouping unit collects various descriptions of the pictorial representation into selected groups. An attribute assigning unit then assigns attributes to the groups. The attributes may include group hierarchy, constraints of motion, color, texture or other features. The modified database is then communicated to a data coupling unit which couples real world data to the groups. Finally, a rendering unit renders the virtual world which looks and functions according to the specified attributes and the real world data.
    Type: Grant
    Filed: September 23, 1998
    Date of Patent: March 31, 2009
    Assignee: Sun Microsystems, Inc.
    Inventors: Dan D. Browning, Ethan D. Joffe, Jaron Z. Lanier