Patents Examined by Xia L Cross
  • Patent number: 11335615
    Abstract: Described herein are wafer accommodation containers. A wafer accommodation container (1) includes: a container body having one end that is provided with an opening (11) and another end that is provided with a mount element (12) on which wafers are stacked, the mount element (12) facing the opening (11); a cover (20) to cover the opening (11); and a connection mechanism (30) to detachably connect the container body (10) and the cover (20).
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: May 17, 2022
    Assignee: ACHILLES CORPORATION
    Inventors: Masayuki Nishijima, Kenichi Hirose
  • Patent number: 11335880
    Abstract: A display includes a display section including a flexible base and an image display layer that is supported by the flexible base and displays an image by utilizing an organic light-emitting phenomenon, in which the display section has a display surface on which the image is to be displayed, a back surface located opposite to the display surface, and a side surface located between the display surface and the back surface and coupled to each of the display surface and the back surface, and a protector provided along at least a portion of the side surface of the display section. The protector includes a metal layer and covers a region extending from a portion of the display surface through the side surface to a portion of the back surface.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: May 17, 2022
    Inventors: Takeshi Yamamoto, Soya Araki, Yoshinori Tachikawa, Yoichiro Eshita, Yohei Azuma, Hayato Niwa
  • Patent number: 11329097
    Abstract: An embodiment provides a semiconductor device including a light-emitting structure including a plurality of light-emitting portions disposed at a side and a plurality of second light-emitting portions disposed at another side, a plurality of first connection electrodes configured to electrically connect the plurality of first light-emitting portions, a plurality of second connection electrodes configured to electrically connect the plurality of second light-emitting portions, a first pad disposed on the plurality of first light-emitting portions, and a second pad disposed on the plurality of second light-emitting portions. The first pad includes a plurality of 1-2 pads extending toward the second pad. The second pad includes a plurality of 2-2 pads extending toward the first pad. The first connection electrode includes a region between the plurality of 1-2 pads in a thickness direction of the light-emitting structure.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: May 10, 2022
    Assignee: SUZHOU LEKIN SEMICONDUCTOR CO., LTD.
    Inventors: Woo Sik Lim, Jae Won Seo, Jin Kyung Choi, Youn Joon Sung, Jong Hyun Kim, Hoe Jun Kim
  • Patent number: 11329148
    Abstract: A semiconductor device includes a substrate. The semiconductor device includes an AlN seed layer in direct contact with the substrate. The AlN seed layer includes an AlN first seed sublayer, and an AlN second seed sublayer, wherein a portion of the AlN seed layer closest to the substrate includes carbon dopants and has a different lattice structure from a substrate lattice structure. The semiconductor device includes a graded layer in direct contact with the AlN seed layer. The graded layer includes a first graded sublayer including AlGaN, a second graded sublayer including AlGaN, and a third graded sublayer including AlGaN. The semiconductor device includes a channel layer over the graded layer. The semiconductor device includes an active layer over the channel layer, wherein the active layer has a band gap discontinuity with the channel layer.
    Type: Grant
    Filed: November 18, 2019
    Date of Patent: May 10, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Ming Chen, Po-Chun Liu, Chung-Yi Yu, Chia-Shiung Tsai, Ru-Liang Lee
  • Patent number: 11329083
    Abstract: An image sensor package is provided. The image sensor package comprises a package substrate, and an image sensor chip arranged over the package substrate. The integrated circuit device further comprises a protection layer overlying the image sensor chip having a planar top surface and a bottom surface lining and contacting structures under the protection layer, and an on-wafer shield structure spaced around a periphery of the image sensor chip. The height of the image sensor package can be reduced since a discrete cover glass or an infrared filter and corresponding intervening materials are no longer needed since being replaced by the build in protection layer. The size of the image sensor package can be reduced since a discrete light shield and corresponding intervening materials are no longer needed since being replaced by the build in on wafer light shield structure.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hau Wu, Chun-Hao Chuang, Kazuaki Hashimoto, Keng-Yu Chou, Wei-Chieh Chiang, Cheng Yu Huang
  • Patent number: 11276587
    Abstract: An apparatus for and a method of bonding a first substrate and a second substrate are provided. In an embodiment a first wafer chuck has a first curved surface and a second wafer chuck has a second curved surface. A first wafer is placed on the first wafer chuck and a second wafer is placed on a second wafer chuck, such that both the first wafer and the second wafer are pre-warped prior to bonding. Once the first wafer and the second wafer have been pre-warped, the first wafer and the second wafer are bonded together.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: March 15, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hui Huang, Chun-Han Tsao, Sheng-Chau Chen, Yeur-Luen Tu, Chia-Shiung Tsai, Xiaomeng Chen
  • Patent number: 11271140
    Abstract: A method for manufacturing a plurality of surface mounted optoelectronic devices and a surface mounted optoelectronic device are disclosed. In an embodiment, a surface mounted optoelectronic device includes a transparent base body having a mounting rear side, a radiation exit side opposite the mounting rear side, and mounting side surfaces which are each disposed transversely to the radiation exit side, a semiconductor layer sequence disposed laterally to at least one mounting side surface and a terminal contact extending from the at least one mounting side surface to the mounting rear side, wherein the semiconductor layer sequence includes an active region configured to emit radiation so that the radiation decouples from the surface mounted optoelectronic device via the radiation exit side of the base body.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: March 8, 2022
    Assignee: OSRAM OLED GMBH
    Inventor: Siegfried Herrmann
  • Patent number: 11251124
    Abstract: An integrated circuit (IC) structure includes a power rail oriented in a power rail direction and first metal segments above the power rail, oriented in a first metal level direction perpendicular to the power rail direction. First vias positioned between the power rail and the first metal segments are positioned at locations where first metal segments overlap the power rail. A second metal segment is positioned above the first metal segments, overlaps the power rail, and is oriented in the power rail direction. Second vias are positioned above the first vias between the first metal segments and the second metal segments, and a power strap is positioned above the second metal segment. The power strap is electrically connected to the power rail, each first metal segment of the plurality of first metal segments has a minimum width, and the power strap has a width greater than a minimum width.
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: February 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Hiranmay Biswas, Chi-Yeh Yu, Chung-Hsing Wang, Kuo-Nan Yang, Stefan Rusu, Chin-Shen Lin
  • Patent number: 11233032
    Abstract: Embodiments of mechanisms for forming a package are provided. The package includes a substrate and a contact pad formed on the substrate. The package also includes a conductive pillar bonded to the contact pad through solder formed between the conductive pillar and the contact pad. The solder is in direct contact with the conductive pillar.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yeong-Jyh Lin, Hsin-Hung Liao, Chien-Ling Hwang, Bor-Ping Jang, Hsiao-Chung Liang, Chung-Shi Liu
  • Patent number: 11232975
    Abstract: Various embodiments of the present application are directed to a method for forming a semiconductor-on-insulator (SOI) substrate without bond interface voids and/or without delamination between layers. In some embodiments, a first high ? bonding structure is formed over a handle substrate. A device layer is formed over a sacrificial substrate. Outer most sidewalls of the device layer are between outer most sidewalls of the sacrificial substrate. A second high ? bonding structure is formed over the device layer. The first high ? bonding structure is bonded to the second high ? bonding structure, such that the device layer is between the sacrificial substrate and the handle substrate. A first removal process is performed to remove the sacrificial substrate. The first removal process comprises performing a first etch into the sacrificial substrate until the device layer is reached.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: January 25, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Min-Ying Tsai, Yeur-Luen Tu
  • Patent number: 11222937
    Abstract: A display unit includes: a drive wire; a planarization layer covering the drive wire and having a connection hole; a relay electrode provided on the planarization layer and configured to be electrically connected to the drive wire through the connection hole; a filling member made of an insulating material and provided in the connection hole; a first partition wall made of a same material as that of the filling member and covering an end of the relay electrode; a first electrode covering the filling member and configured to be electrically connected to the relay electrode; a second electrode facing the first electrode; and a functional layer located between the first electrode and the second electrode, the functional layer including a light-emitting layer.
    Type: Grant
    Filed: September 17, 2018
    Date of Patent: January 11, 2022
    Assignee: Sony Group Corporation
    Inventors: Shinichi Teraguchi, Eisuke Negishi, Shuji Kudo
  • Patent number: 11199750
    Abstract: In accordance with some embodiments of the disclosure, an array substrate and a related liquid crystal display device are provided. The array substrate can include a plurality of pixel electrodes arranged on a base substrate, and a conductive opaque line arranged between two neighboring pixel electrodes and overlapping with each of the two neighboring pixel electrodes along a width direction of the conductive opaque line.
    Type: Grant
    Filed: April 3, 2019
    Date of Patent: December 14, 2021
    Assignees: FUZHOU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xibin Shao, Lifeng Lin, Honglin Zhang, Hongming Zhan, Yu Ma, Kui Zhang, Chao Tian, Zhe Li
  • Patent number: 11195891
    Abstract: A display device includes a display panel including a lower surface, an upper surface facing the lower surface, and a first area, a first film positioned below the lower surface and provided with a film groove defined therein overlapping with the first area, a second film disposed on the upper surface, and an adhesive layer disposed between the lower surface of the display panel and the first film and provided with an adhesive groove defined therein overlapping with the first area. The first area extends across the display panel along a first direction, one side surface of the adhesive groove is defined by one line when viewed in a cross section taken along a second direction crossing the first direction, and one side surface of the film groove is defined by two or more lines when viewed in the cross section taken along the second direction.
    Type: Grant
    Filed: August 17, 2020
    Date of Patent: December 7, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Junghoon Han, Jihoon Kim, Daeseung Mun
  • Patent number: 11189589
    Abstract: A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a metallization structure with a top surface. A conductive pad is over the top surface. An upper passivation layer is over the top surface and the conductive pad and includes a first implanted region. A polymer layer is over the upper passivation layer and the conductive pad. A conductive via penetrates through the upper passivation layer and the polymer layer, and electrically coupled to the conductive pad. A method for manufacturing a semiconductor structure is also provided.
    Type: Grant
    Filed: September 25, 2019
    Date of Patent: November 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Ching Shan Wang, Cheng Hsun Hsieh
  • Patent number: 11177376
    Abstract: III-N semiconductor heterostructures on III-N epitaxial islands laterally overgrown from a mesa of a silicon substrate. An IC may include a III-N semiconductor device disposed on the III-N epitaxial island overhanging the silicon mesa and may further include a silicon-based MOSFET monolithically integrated with the III-N device. Lateral epitaxial overgrowth from silicon mesas may provide III-N semiconductor regions of good crystal quality upon which transistors or other active semiconductor devices may be fabricated. Overhanging surfaces of III-N islands may provide multiple device layers on surfaces of differing polarity. Spacing between separate III-N islands may provide mechanical compliance to an IC including III-N semiconductor devices. Undercut of the silicon mesa may be utilized for transfer of III-N epitaxial islands to alternative substrates.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: November 16, 2021
    Assignee: Intel Corporation
    Inventors: Sansaptak Dasgupta, Han Wui Then, Sanaz K. Gardner, Marko Radosavljevic, Seung Hoon Sung, Benjamin Chu-Kung, Robert S. Chau
  • Patent number: 11158579
    Abstract: A semiconductor package includes a frame having a cavity and having a wiring structure connecting first and second surfaces opposing each other; a connection structure disposed on the first surface of the frame and including a first redistribution layer connected to the wiring structure; a semiconductor chip disposed in the cavity and having a connection pad connected to the first redistribution layer; an encapsulant encapsulating the semiconductor chip; and a second redistribution layer having a redistribution pattern and a connection via connecting the wiring structure and the redistribution pattern. The connection via includes a first via connected to the wiring structure and a second via disposed on the first via and connected to the redistribution pattern, a lower surface of the second via has an area larger than an area of an upper surface of the first via.
    Type: Grant
    Filed: September 5, 2019
    Date of Patent: October 26, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Han Ul Lee, Young Gwan Ko
  • Patent number: 11158778
    Abstract: A light-emitting device is disclosed, including: a substrate; a light-emitting diode (LED) formed on a first surface of the substrate, the LED being arranged to emit primary light; a fence disposed on a second surface of the substrate, the fence including a plurality of walls arranged to define a cell; a light-converting structure disposed in the cell, the light-converting structure being arranged to convert at least a portion of the primary light to secondary light having a wavelength that is different from the wavelength of the primary light; and a reflective element formed on one or more outer surfaces of the walls of the fence, such that the reflective element and the light-converting structure are disposed on opposite sides of the walls of the fence.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: October 26, 2021
    Assignee: Lumileds LLC
    Inventors: Brendan Jude Moran, Lex Kosowsky
  • Patent number: 11152442
    Abstract: By using an a-Si layer with low electron mobility in a TFT for driving an organic EL display device, the present invention solves problems stemming from uneven laser irradiation and suppresses the occurrence of non-uniform color and luminance. In the present invention, a first conductor film (26a) forming a drain electrode and a second conductor film (25a) forming a source electrode are disposed such that respective portions (26a1 . . . , 25a1 . . . ) of the first conductor film (26a) and the second conductor film (25a) are arranged in an alternating manner along a prescribed direction.
    Type: Grant
    Filed: March 28, 2018
    Date of Patent: October 19, 2021
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: Katsuhiko Kishimoto, Yukiya Nishioka
  • Patent number: 11133381
    Abstract: In a general aspect, a semiconductor device can include a semiconductor region of a first conductivity type and a well region of a second conductivity type. The well region can be disposed in the semiconductor region. An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The semiconductor device can further include at least one dielectric region disposed in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: September 28, 2021
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Shengling Deng, Dean E. Probst, Zia Hossain
  • Patent number: 11133209
    Abstract: Disclosed is a transfer head for transferring micro-LEDs from a first substrate to a second substrate, particularly, using a vacuum adsorption method. The transfer head includes a porous member having a plurality of pores, in which the micro-LEDs are transferred by creating or releasing a vacuum pressure in the pore of the porous member.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: September 28, 2021
    Assignee: POINT ENGINEERING CO., LTD.
    Inventors: Bum Mo Ahn, Seung Ho Park, Sung Hyun Byun