Abstract: A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage modifier (CVM) coupled to the PMIC. The CVM is configured to receive the primary supply voltage of the memory sub-system as an input and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the first MPSV is not higher than the uppermost PMIC supply voltage.
Abstract: A program method of a nonvolatile memory device including receiving a write address and write data, generating a seed corresponding to the write address, generating a random sequence by using the seed, randomizing the write data by using the random sequence, and programming the randomized write data to a memory area corresponding to the write address may be provided. The seed may provide state shaping variable depending on a location of a word line, at which the received write data is to be programmed.
Abstract: According to one embodiment, a memory system includes a semiconductor memory having a plurality of memory cells and a memory controller that controls the semiconductor memory to perform write and read operations and a read operation. The memory controller causes the semiconductor memory to execute a first write operation using a first voltage, detects, in a read operation, first memory cells among the plurality of memory cells that have a threshold voltage higher than a voltage value corresponding to data to be stored and sets a second voltage used for a second write operation after the first write operation based on a detection result of the first memory cells.
Abstract: Memory might include a controller configured to cause the memory to apply a boost voltage level to each capacitance of a plurality of capacitances each connected to a respective node of a sense circuit, selectively discharge each of the nodes through respective memory cells selected for a sense operation, measure a current demand of the plurality of capacitances while each of the nodes is connected to its respective memory cell, determine a deboost voltage level in response to the measured current demand, apply the deboost voltage level to each capacitance of the plurality of capacitances, and determine a respective data state of each memory cell of the plurality of memory cells while the deboost voltage level is applied to each capacitance of the plurality of capacitances.
Abstract: The present disclosure relates to a memory device may include a plurality of memory cells coupled to a selected word line and to be programmed to one of first to n-th program states distinguished from each other based on threshold voltages thereof, a sensing latch storing data sensed from a bit line coupled to one memory cell, a pre-latch storing pre-verify information and a plurality of data latches storing data to be stored in the one memory cell, wherein at least one data latch stores main verify information on the main verify voltage during verify operations for the first program state to a threshold program state among the first to n-th program states until the verify operation for the threshold program state passes, and wherein the pre-latch stores the main verify information on the n-th program state after the verify operation for the threshold program state passes.
Abstract: A memory device includes a communication circuit configured to communicate a first signal and a second signal; and a selection mechanism coupled to the communication circuit and configured to select between operating the communication circuit the first signal and the second signal (1) independent signals for separate memory operations or (2) a complementary set for a memory operation.
Abstract: A flash memory system includes a memory controller, flash memory, power supply circuit, and control circuit. The power supply circuit includes a power supply terminal fed with external power, a step-up circuit for boosting a first voltage associated with the external power and thereby generating a second voltage higher than the first voltage, a capacitor charged at the second voltage, and a first step-down circuit for lowering the second voltage and thereby generating a third voltage lower than the second voltage, and supplying the generated third voltage to the flash memory as the operating voltage. The control circuit includes a circuit for controlling the active or inactive state of the flash memory based on the level of the third voltage, and a circuit for controlling the active or inactive state of the memory controller based on both the levels of the voltage of the external power and the third voltage.
Abstract: According to one embodiment, a semiconductor integrated circuit includes a first circuit, a second circuit, a third circuit, and a switch circuit. The second circuit is different from the first circuit. The third circuit is configured to adjust a timing of an edge of a signal. The switch circuit is configured to connect the third circuit to the first circuit in a case where a first signal is output from the first circuit to an outside of the semiconductor integrated circuit, and configured to connect the third circuit to the second circuit in a case where a second signal is output from the second circuit to the outside, the second signal being different from the first signal.
Abstract: A memory interface circuit includes a first output buffer circuit, a second output buffer circuit, a switching element, and a control circuit. The first output buffer circuit includes a first output node. The second output buffer circuit includes a second output node. The switching element is electrically connected to the first output node and the second output node, and is controlled to switch electrical connection states between the first output node and the second output node. The control circuit controls the switching element.
Abstract: Provided herein is a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes: a memory cell array including a plurality of word lines; a peripheral circuit coupled to the memory cell array through the plurality of word lines and configured to apply a program voltage to a selected word line of the plurality of word lines during a program operation and apply a pass voltage to unselected word lines of the plurality of word lines; and control logic configured to control the peripheral circuit to apply a first pass voltage to word lines adjacent to the selected word line among the unselected word lines during a first program operation of the program operation and apply a second pass voltage to the word lines adjacent to the selected word line during a second program operation of the program operation.
Abstract: Devices, systems, and methods for reducing sensing delays for a non-volatile memory reading circuit may include operations for pre-charging a plurality of bit lines coupling a memory array having multiple bit cells with a sensing amplifier. Upon receiving a read request identifying a given bit cell in the memory array, the addressed bit line is decoupled from a bias voltage. The addressed bit line corresponds to the given bit cell and is selected from the plurality of bit lines. With the decoupling from the bias voltage, the addressed bit lines are coupled to the sensing amplifier. After a sensing circuit delay, data stored in the given bit cell is provided to the sensing amplifier via the addressed bit lines coupled to the sensing amplifier. The data stored in the given bit cell may then be interpreted by the sensing amplifier and a corresponding data output signal is generated.
Abstract: Disclosed is a data storage circuit that stores target input data inputted to a data input terminal and outputs the stored data as target output data through a data output terminal. The data storage circuit includes a clock control circuit that outputs a master clock signal and a slave clock signal based on a reference clock signal, a master latch circuit that takes the target input data based on the master clock signal, holds the taken data, and outputs the taken data as master output data, a slave latch circuit that takes the master output data based on the slave clock signal, holds the taken data, and outputs the taken data as slave output data, and an output data generation circuit that generates the target output data.
Abstract: Embodiments disclosed herein relate to level shifters of a memory device. Specifically, the level shifters include a first series arrangement of transistors to offset a first transistor. The level shifters also include a second series arrangement of transistors to offset a second transistor. The first series arrangement is opposite the second series arrangement. The output of the first series arrangement is coupled to a first pull-up transistor and configured to cut off a pull-up of the first pull-up transistor to a first voltage. The output of the second series arrangement is coupled to a second pull-up transistor and configured to cut off a pull-up of the second pull-up transistor to the first voltage. The first series arrangement and the second series arrangement are coupled to a second voltage at different times. The series arrangements of transistors enable faster level shifting over conventional level shifters.
Abstract: A memory device is provided. The memory device includes a first transistor and a second transistor connected in series with the first transistor. The second transistor is programmable between a first state and a second state. A bit line connected to the second transistor. A sense amplifier connected to the bit line. The sense amplifier is operative to sense data from the bit line. A feedback circuit connected to the sense amplifier, wherein the feedback circuit is operative to control a bit line current of the bit-line.
Abstract: The present disclosure includes apparatuses and methods related to refresh circuitry. An example apparatus can include a memory array including a main portion and a redundant portion. The apparatus can include refresh circuitry configured to, responsive to a determination of a hammering event, refresh at least a portion of the redundant portion.
Abstract: Memory devices and systems with partial array refresh control over memory regions in a memory array, and associated methods, are disclosed herein. In one embodiment, a memory device includes a memory array having a first memory region and a second memory region. The memory device is configured to write data to the memory array in accordance with a programming sequence by initially writing data to unutilized memory cells of the first memory region before initially writing data to unutilized memory cells of the second memory region. The memory device is further configured to determine that the data stored on the first and/or second memory regions is not consolidated, and to consolidate at least a portion of the data by rewriting the portion of the data to physically or logically contiguous memory cells of the first memory region and/or the second memory region.
July 27, 2020
Date of Patent:
March 15, 2022
Micron Technology, Inc.
Dale H. Hiscock, Debra M. Bell, Michael Kaminski, Joshua E. Alzheimer, Anthony D. Veches, James S. Rehmeyer
Abstract: A memory system may include a memory device and a memory controller. The memory device may include memory cells. The memory controller may estimate and use an read voltage to distinguish one or more memory cells corresponding to a first threshold voltage distribution from one or more memory cells corresponding to a second threshold voltage distribution, the read voltage being estimated based on standard deviations and average threshold voltages of the first and the second threshold voltage distributions and probability density functions corresponding to the first and the second threshold voltage distributions, respectively. The memory controller may be structured and operable to calculate the standard deviation of the first threshold voltage distribution, based on a first probability area distinguished by a first target read voltage, a second probability area distinguished by a second target read voltage, and inverse Q-function values corresponding to the first and the second probability areas.
Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The device is configured to execute a first operation, a second operation, and a third operation to write data into the first memory cell. In the first operation, a first voltage is applied to the second word line. In the second operation, after the first operation, a second voltage higher than the first voltage is applied to the second word line. In the third operation, after the second operation, a third voltage higher than the second voltage is applied to the first word line, and a fourth voltage lower than both the second voltage and the third voltage is applied to the second word line.
Abstract: A nonvolatile semiconductor storage device includes a first channel layer including a first drain-side select transistor, a first source-side select transistor, and a first memory cell transistor, a second channel layer including a second drain-side select transistor, a second source-side select transistor, and a second memory cell transistor, a word line that functions as a gate electrode of the first and second memory cell transistors, and a controller. When a read operation is executed on the first memory cell transistor, the controller turns on the second drain-side select transistor and the second source-side select transistor, supplies a first voltage to the word line in a state where the first drain-side select transistor and the first source-side select transistor are turned off, and then, supplies a second voltage to the word line in a state where the first drain-side select transistor and the first source-side select transistor are turned on.
Abstract: A memory device includes: a memory bit cell; a write circuit, coupled to the memory bit cell, and configured to use a first voltage to transition the memory bit cell to a first logic state by changing a respective resistance state of the memory bit cell, and compare a first current flowing through the memory bit cell with a first reference current; and a control logic circuit, coupled to the write circuit, and configured to determine whether the first logic state is successfully written into the memory bit cell based on a read-out logic state of the memory bit cell and the comparison between the first current and first reference current.