Abstract: A control circuit controls a column decoder and a row decoder to perform reprogramming where, before the count of reprogramming operations involving erasures, each targeting one of a plurality of memory cells included in a memory cell array, reaches a predetermined number, a first extent (e.g. a sub-block) including the targeted memory cell and being smaller than the entire extent of the memory cell array is used as the unit of reprogramming, and when the count of reprogramming operations reaches the predetermined number, a second extent (e.g. the memory cell array corresponding to one sector) including the targeted memory cell and being larger than the first extent is used as the unit of reprogramming, and resets the count of reprogramming operations each time it reaches the predetermined number.

Abstract: Apparatuses and methods for reducing row address (RAS) to column address (CAS) delay are disclosed. An example apparatus includes a memory including a sense amplifier configured to, during a precharge phase, couple a first gut node of the sense amplifier to a second gut node of the sense amplifier and to a precharge voltage while the first gut node and the second gut node are coupled to a first digit line and a second digit line, respectively, at a first time. The sense amplifier is further configured to, during the precharge phase, decouple the first gut node from the first digit line and decouple the second gut node from the second digit line at a second time that is after the first time. The sense amplifier is further configured to transition to an activation phase in response to an activate command at a third time after the second time to perform a sense operation.

Abstract: There is provided a memory unit comprising an array of memory cells and a driver circuit configured to output an output address signal that addresses a portion/subset of the array of memory cells. The driver circuit comprises a logic gate that is configured to receive one or more input address signals and to provide an output address signal in dependence upon the one or more input address signals, and wherein the logic gate is configured to output a drive voltage provided by a first of the one or more input address signals as the output address signal when the output of the logic gate is true/high.

Abstract: A memory sub-system includes a power management integrated circuit (PMIC) compatible with operation at an uppermost PMIC supply voltage that is lower than a primary supply voltage of the memory sub-system. The PMIC is configured to output multiple voltages for operation of the memory sub-system based on a PMIC supply voltage. The memory sub-system further includes a capacitive voltage modifier (CVM) coupled to the PMIC. The CVM is configured to receive the primary supply voltage of the memory sub-system as an input and provide a first modified primary supply voltage (MPSV) to the PMIC as the PMIC supply voltage, where the first MPSV is not higher than the uppermost PMIC supply voltage.

Abstract: A semiconductor device includes a drive control circuit and a write control circuit. The drive control circuit generates a pre-drive control signal and a drive control signal based on a latch command and generates a pattern drive control signal based on a pattern latch command. The write control circuit stores drive data generated from data inputted based on the pre-drive control signal and the drive control signal or stores the drive data driven to a predetermined logic level based on the pattern drive control signal.

Abstract: A semiconductor memory device includes a differential waveform shaping circuit including first and waveform shaping circuits connected in parallel. The first waveform shaping circuit has a first inverting amplifier, and two inverters connected in series. The first inverting amplifier inverts and differentially amplifies an input signal having a rectangular waveform. Then, the output of the first inverting amplifier is passed through the two inverters. The second waveform shaping circuit has a first inverter, a second inverting amplifier, and a second inverter connected in series. The second inverting amplifier inverts and differentially amplifies the output signal from the first invertor, and the second inverter inverts the output signal from the second inverting amplifier. The differential waveform shaping circuit generates an output signal by averaging the output signal from the first waveform shaping circuit and the output signal from the second waveform shaping circuit.

Abstract: A memory device controls a page buffer to ensure the reliability of data. The memory device includes: a memory cell array including a plurality of memory cells configured for storing data; first and second page buffers respectively including main latches and cache latches, which are coupled to a bus, the first and second page buffers being connected to the memory cell array respectively through bit lines coupled to the main latches; and control logic including a bus precharge controller for differently setting a voltage level of the bus, based on a distance between a reference position and the first page buffer and a distance between the reference position and the second page buffer, for precharging of the bus for transmitting data of a cache latch included in each of the first and second page buffers to a corresponding main latch.

Abstract: Methods and apparatuses for single level cell caching are described. According to one example, a method includes receiving, at a memory device, a first set of data to be stored in a lower page of multilevel memory cells, storing the first set of data in a page of single level memory cells, storing the first set of data in the lower page of the multilevel memory cells, receiving, at the memory device, a second set of data to be stored in an upper page of the multilevel memory cells, and storing the second set of data directly in the upper page of the multilevel memory cells.

Abstract: A data storage device may include: a storage; and a controller configured to control data input/output for the storage, wherein the controller comprises a power state manager configured to detect a failure of an operation that is performed in the storage based on a program, erase or read command, transfer a power state check request command to the storage when the failure is detected, and reset the storage based on whether the storage transfers a return signal in response to the power state check request command.

Abstract: Techniques for negative voltage generation for a computer memory are described herein. An aspect includes enabling a first negative word line voltage (VWL) clock generator. Another aspect includes providing, by the first VWL clock generator, based on a clock signal, a first pump clock signal to a first VWL pump, and a second pump clock signal to a second VWL pump. Another aspect includes generating a VWL based on the first VWL pump and the second VWL pump, wherein the VWL is provided to a word line driver of a computer memory module. Another aspect includes comparing the VWL to a VWL reference voltage. Another aspect includes, based on the VWL being below the VWL reference voltage, disabling the first VWL clock generator, wherein the first VWL pump and the second VWL pump are disabled based on disabling the first VWL clock generator.

Abstract: To use larger capacity TCAMs while avoiding various packaging and power management issues of TCAMs, pre-processing can be performed on TCAM lookup requests to intelligently pipeline lookup requests according to a defined power budget that is based on TCAM and power supply specifications. Dividing lookup requests based on a power budget smooths the instantaneous current demand and dynamic power demand. This intelligent pre-processing of lookup requests allows lookup requests that satisfy a power budget based threshold to still complete within a single clock cycle while nominally reducing performance for those lookup requests that would not satisfy the power budget based threshold. When a lookup request will not satisfy the power budget based threshold, the lookup request is split into searches targeting different memory blocks of the TCAM.

Abstract: The apparatus includes a row hammer refresh (RHR) circuit configured to steal a first refresh cycle to implement a first RHR segment; and steal a second refresh cycle after one or more operating cycles, the second refresh cycle to implement a second RHR segment.

Abstract: A storage device with a charge trapping (CT) based memory may include improved data retention performance. Data retention problems, such as charge loss in CT memory may increase for a particular programmed state when a neighboring state is at erased state. Modifying the erase state with post write erase conditioning (PWEC) by pushing up deeply erased states can reduce the lateral charge movement and improve high temperature data retention. In particular, the erase state may be reprogrammed such that the erase distribution is tighter with a higher voltage.

Abstract: A semiconductor memory device is provided with a row control circuit, in order to dissolve a Row Hammer issue. The row control circuit is configured to: (A) latches one of (a) a target address upon issuing of an ACTIVE command to the semiconductor memory device, and (b) a row address of a victim cell in which data of a memory cell is affected by the target address, as a victim address by using a predetermined row address latch method; and then, (B) refreshes the victim cell having the victim address by a predetermined refresh method upon issuing of a REFRESH command.

Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.

Abstract: A memory device includes a memory array including a first communication circuit element configured to communicate a first signal between components in the memory device; a second communication circuit element configured to communicate a second signal between the components in the memory device; and a configurable grouping mechanism coupled to the first communication circuit element and the second communication circuit element, the configurable grouping mechanism configured to select between: operating the first communication circuit element and the second communication circuit element independent of each other, where in the first signal and the second signal are independent signals, and operating the first communication circuit element and the second communication circuit element as a group, wherein the first signal corresponds to the second signal.

Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

Abstract: Apparatuses and methods for configurable memory array bank architectures are described. An example apparatus includes a mode register configured to store information related to bank architecture and a memory array including a plurality of memory banks. The plurality of memory banks are configured to be arranged in a bank architecture based at least in part on the information related to bank architecture stored in the mode register.

Abstract: A semiconductor device may include a plurality of memory banks, a plurality of mode registers that may control an operational mode associated with each of the plurality of memory banks, and a set of global wiring lines coupled to each of the plurality of mode registers. The set of global wiring lines may include a first global wiring line to transmit data to each of the plurality of mode registers, a second global wiring line to transmit an address signal to each of the plurality of mode registers, a third global wiring line to transmit a read command signal to each of the plurality of mode registers, and a fourth global wiring line to transmit a write command signal to each of the plurality of mode registers.

Abstract: The disclosure provides a semiconductor memory device that improves the reliability of data reading and achieves good area efficiency. A variable resistance memory of the disclosure includes a memory array, a row decoder, a column decoder, a writing part, and a reading part. The memory array includes a plurality of memory cells. The row decoder selects the memory cells in a row direction. The column decoder selects the memory cells in a column direction. The writing part writes identical data to a pair of memory cells that is selected. The reading part reads the data stored in the pair of memory cells that is selected. The reading part includes a sense amplifier that compares a total of the currents respectively flowing through the pair of memory cells with a reference value.