Patents Examined by Xiaochun L Chen
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Patent number: 11189359Abstract: Methods, systems, and devices for techniques for data programming are described for programming data to a memory system using a second programming mode associated with a higher error rate than a first programming mode. The second programming mode may include skipping one or more voltage calibration procedures included in the first programming mode, as well as performing one or more data verification procedures once a larger set of the data is programmed. The second programming mode may also include using a higher programming voltage pulse to program data and the programming pulse may last for a longer period of time than a programming pulse for the first programming mode. A memory system may receive data, determine to write the data to a memory device using the second programming mode, write the data using the second programming mode, and verify whether the data satisfies an error threshold.Type: GrantFiled: June 30, 2020Date of Patent: November 30, 2021Assignee: Micron Technology, Inc.Inventor: Giuseppe Cariello
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Patent number: 11189355Abstract: A first group of memory cells of a memory device can be subjected to a particular quantity of program/erase cycles (PECs) in response to a programming operation performed on a second group of memory cells of the memory device. Subsequent to subjecting the first group of memory cells to the particular quantity of PECs, a data retention capability of the first group of memory cells can be assessed.Type: GrantFiled: August 25, 2020Date of Patent: November 30, 2021Assignee: Micron Technology, Inc.Inventors: Vamsi Pavan Rayaprolu, Giuseppina Puzzilli, Karl D. Schuh, Jeffrey S. McNeil, Jr., Kishore K. Muchherla, Ashutosh Malshe, Niccolo' Righetti
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Patent number: 11189328Abstract: A semiconductor device includes an input control circuit and an internal command generation circuit. The input control circuit is synchronized with a first pulse of an internal clock signal to generate an internal chip selection signal and a first internal command/address signal from a chip selection signal and a command/address signal. In addition, the input control circuit is synchronized with a second pulse of the internal clock signal to inhibit generation of the internal chip selection signal. The internal command generation circuit generates a first active command and a second active command which are sequentially enabled when the internal chip selection signal and the first internal command/address signal have a predetermined logic level combination.Type: GrantFiled: September 24, 2020Date of Patent: November 30, 2021Assignee: SK hynix Inc.Inventor: Noh Hyup Kwak
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Patent number: 11176998Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.Type: GrantFiled: May 26, 2020Date of Patent: November 16, 2021Assignee: KIOXIA CORPORATIONInventor: Hiroshi Maejima
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Patent number: 11163495Abstract: Apparatuses and methods are provided for processing in memory. An example apparatus comprises a host and a processing in memory (PIM) capable device coupled to the host via an interface comprising a sideband channel. The PIM capable device comprises an array of memory cells coupled to sensing circuitry and is configured to perform bit vector operations on data stored in the array, and the host comprises a PIM control component to perform virtual address resolution for PIM operations prior to providing a number of corresponding bit vector operations to the PIM capable device via the sideband channel.Type: GrantFiled: April 17, 2020Date of Patent: November 2, 2021Assignee: Micron Technology, Inc.Inventors: Perry V. Lea, Timothy P. Finkbeiner
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Patent number: 11158645Abstract: According to one embodiment, a semiconductor memory device including a first memory cell; a word line; a bit line; a row decoder; a sense amplifier including a latch circuit; a data register; and a control circuit capable of suspending a write operation during the write operation of the first memory cell to perform a read operation of the first memory cell. In a read operation of the first memory cell performed while suspending the write operation, the row decoder applies a read voltage to the word line, and the sense amplifier transmits data read from the first memory cell to the data register as read data when writing to the first memory cell is completed, and transfers write data held by the latch circuit to the data register as the read data when the writing is not completed.Type: GrantFiled: January 22, 2020Date of Patent: October 26, 2021Assignee: KIOXIA CORPORATIONInventor: Koichiro Yamaguchi
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Patent number: 11152074Abstract: A memory device includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and connected to the memory cell region by the first and second metal pads, and a memory cell array in the memory cell region and including cell strings. The cell strings include memory cells, word lines and dummy lines connected to the memory cells, bit lines connected to one side of the cell strings, and a ground selection line connected to the cell strings. The memory device further includes control logic in the peripheral circuit region and including a precharge control circuit that controls a precharge on partial cell strings among the cell strings and controls data program steps on the memory cells, and a row decoder in the peripheral circuit region that activates at least some of the word lines based on control of the control logic.Type: GrantFiled: August 20, 2020Date of Patent: October 19, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Sung-Min Joe, Kang-Bin Lee
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Patent number: 11145348Abstract: The disclosure provides a circuit structure and method for memory storage using a memory cell and magnetic random access memory (MRAM) stack. A circuit structure includes a memory cell having a first latch configured to store a digital bit, a first diode coupled to the first latch, and a first magnetic random access memory (MRAM) stack coupled to the first latch of the memory cell through the first diode. The first MRAM stack includes a first layer and a second layer each having a respective magnetic moment. The magnetic moment of the second layer is adjustable between a parallel orientation and an antiparallel orientation with respect to the magnetic moment of the first layer. Further, the magnetic anisotropy of the second layer can be modified through application of an applied voltage (VCMA effect). A spin Hall electrode is directly coupled to the first MRAM stack.Type: GrantFiled: May 11, 2020Date of Patent: October 12, 2021Assignee: GlobalFoundries U.S. Inc.Inventors: Akhilesh R. Jaiswal, Ajey Poovannummoottil Jacob, Steven R. Soss
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Patent number: 11145370Abstract: Apparatuses and methods for segmented SGS lines are described. An example apparatus includes a plurality of memory subblocks, a plurality of first select gate control lines, each first select gate control line of the plurality of first select gate control lines configured to couple a memory subblock of the plurality of memory subblocks to a signal line, and a second select gate control line configured to couple the plurality of memory subblocks to a source line.Type: GrantFiled: October 8, 2020Date of Patent: October 12, 2021Assignee: Micron Technology, Inc.Inventors: Feng Pan, Jaekwan Park, Ramin Ghodsi
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Patent number: 11133043Abstract: According to one implementation of the present disclosure, an integrated circuit includes first and second word-line decoder circuitry; one or more core arrays, respective input/output (I/O) circuitry for each of the one or more core arrays, and control circuitry coupled to the first and second word-line decoder circuitries, the one or more core arrays, and the respective I/O circuitries. Also, one or more control signals, activated from one or more control signals generated in the control circuitry, may be configured to select corresponding one or more core arrays of the one or more core arrays.Type: GrantFiled: February 5, 2020Date of Patent: September 28, 2021Assignee: Arm LimitedInventors: Andy Wangkun Chen, Yew Keong Chong, Sriram Thyagarajan
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Patent number: 11133070Abstract: A nonvolatile memory device includes a nonvolatile memory cell including a first cell transistor and a second cell transistor electrically coupled to a bit line in parallel and configured to respectively have a first physical size and a second physical size, a cell transistor selector coupled between the nonvolatile memory cell and a ground voltage terminal to control electrical connections between the first cell transistor and the ground voltage terminal, and between the second cell transistor and the ground voltage terminal, and a read voltage selection circuit suitable for selectively supplying one of a first read voltage and a second read voltage to the bit line.Type: GrantFiled: June 16, 2020Date of Patent: September 28, 2021Assignee: SK hynix system ic Inc.Inventor: Hyun Min Song
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Patent number: 11120848Abstract: A method for operating a plurality of memory cells includes performing a read operation to each of the plurality of memory cells. If at least one memory cell of the plurality of memory cells is determined to be in a programmed state, perform an erasing test operation to the at least one memory cell with an initial erase voltage being applied to the erase line, and perform a verification operation to the at least one memory cell. If the cell current is smaller than the reference current, generate an intermediate erase voltage by adding a step voltage to an erase voltage currently used, and perform the erasing test operation to the at least one memory cell with the intermediate erase voltage being applied to the erase line. Performing the verification operation to the at least one memory cell again.Type: GrantFiled: August 11, 2020Date of Patent: September 14, 2021Assignee: eMemory Technology Inc.Inventor: I-Lang Lin
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Patent number: 11114175Abstract: A Read Only Memory (ROM) cell array includes: a first transistor coupled to a first word line; a second transistor coupled to a second word line; and a third transistor disposed between the first transistor and the second transistor, the third transistor having a first gate terminal permanently coupled to a power rail.Type: GrantFiled: August 6, 2020Date of Patent: September 7, 2021Assignee: QUALCOMM INCORPORATEDInventors: Paramjeet Singh, Bipin Duggal
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Patent number: 11114178Abstract: Technology for physical defect detection in an integrated memory assembly having a control semiconductor die and a memory semiconductor die is disclosed. The control die compares actual current usage during a memory operation (such as a program operation) with expected current usage. In the event that the actual current usage deviates from the expected current usage by more than a threshold, a region of the memory structure is suspected as having a physical defect. For example, the selected word that is connected to the memory cells that were programmed may be suspected as having a physical defect. If a region is suspected as having a physical defect, a data integrity check may be performed in that region. If the data integrity check fails, the region may be marked as ineligible to store data.Type: GrantFiled: June 10, 2020Date of Patent: September 7, 2021Assignee: Western Digital Technologies, Inc.Inventors: Tomer Eliash, Yu-Chung Lien, Alexander Bazarsky, Eran Sharon
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Patent number: 11107514Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a memory cell array of a plurality of memory cells each including a variable resistance element and outputting, to a corresponding bit line, a cell voltage corresponding to a resistance value of the variable resistance element; a driving control circuit operable to control a reference data to be written in a selected memory cell among the memory cells, during a sensing operation; a resistance monitoring circuit operable to receive the cell voltage of the selected memory cell and output a monitoring voltage based on the cell voltage at the bit line, the monitoring voltage corresponding to a change in the resistance value during the sensing operation; and an amplifying circuit operable to amplify the monitoring voltage and output an amplified monitoring voltage as output data.Type: GrantFiled: March 24, 2020Date of Patent: August 31, 2021Assignee: SK hynix Inc.Inventor: Seung-Heon Baek
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Patent number: 11100987Abstract: A selection scheme for crosspoint memory is described. In one example, the selection voltage applied across the memory cell is slowly ramped up. Once the memory cell thresholds, the voltage is reduced to a level for performing the read or write operation. Reducing the voltage once the specific cell has been selected (e.g., thresholds) minimizes the additional transient current which might be generated by further increasing the selection bias applied during read or write operation. The reduction in transient current can lead to an improvement in read disturb and write endurance issues. The selection ramp-rate and bias post-selection can be set differently depending on the cell location inside the memory array to further improve cell performance.Type: GrantFiled: March 26, 2020Date of Patent: August 24, 2021Assignee: Intel CorporationInventors: Davide Mantegazza, Kyung Jean Yoon, John Gorman, Dany-Sebastien Ly-Gagnon
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Patent number: 11094379Abstract: Methods, as well as apparatus configured to perform similar methods, might include programming a plurality of memory cells to a particular data state of a plurality of data states, and, for each memory cell of the plurality of memory cells whose target data state is higher than the particular data state, determining a respective indication of a programming voltage level deemed sufficient to program that memory cell to a respective target threshold voltage corresponding to its respective target data state, and further programming that memory cell using a programming voltage level of a plurality of programming voltage levels corresponding to the respective indication of the programming voltage level deemed sufficient to program that memory cell to the respective target threshold voltage corresponding to its respective target data state.Type: GrantFiled: March 31, 2020Date of Patent: August 17, 2021Assignee: Micron Technology, Inc.Inventor: Aaron S. Yip
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Patent number: 11094355Abstract: A random access memory having a memory array having a plurality of local memory groups, each local memory group including a plurality of bitcells arranged in a bitcell column, a pair of local bitlines operatively connected to the plurality of bitcells, a pair of global read bitlines, a local group read port arranged between the pair of local bitlines and the pair of global read bitlines for selectively accessing one of the local bitlines depending on a state of a selected bitcell, and a local group precharge circuit operatively arranged between the pair of local bitlines.Type: GrantFiled: May 5, 2020Date of Patent: August 17, 2021Assignee: ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE (EPFL)Inventors: William Andrew Simon, Marco Antonio Rios, Alexandre Sébastien Levisse, Marina Zapater, David Atienza Alonso
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Patent number: 11087815Abstract: Readout circuit and magnetic memory are provided. The readout circuit includes a first charging capacitor with one end grounded and another end coupled to an output of a data unit; a first pre-charge module for charging the first charging capacitor; a first discharge control module for controlling a magnitude of a data voltage; a second charging capacitor with one end grounded and another end coupled to an output of a reference unit; a second pre-charge module for charging the second charging capacitor; a second discharge control module for controlling a magnitude of a reference voltage; and a sense amplifier for outputting readout signals.Type: GrantFiled: March 24, 2020Date of Patent: August 10, 2021Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventors: Siwen Zheng, Hao Ni, Tengye Wang, Tao Wang
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Patent number: 11087858Abstract: A memory device comprises, on an integrated circuit or multi-chip module, a memory including a plurality of memory blocks, a controller, and a refresh mapping table in non-volatile memory accessible by the controller. The controller is coupled to the memory to execute commands with addresses to access addressed memory blocks in the plurality of memory blocks. The refresh mapping table has one or more entries, an entry in the refresh mapping table mapping of an address identifying an addressed memory block set for refresh to a backup block address. The controller is responsive to a refresh command sequence with a refresh block address to execute a refresh operation, and is configured to restore mapping of the refresh block address to the backup block address upon power-on of the device, to scan the refresh mapping table for a set entry, and to register the set entry in the refresh mapping table.Type: GrantFiled: July 24, 2020Date of Patent: August 10, 2021Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Shuo-Nan Hung, Chun-Lien Su
