Patents Examined by Xiaochun L Chen
  • Intelligent proactive responses to operations to read data from memory cells
    Patent number: 11081200
    Abstract: A memory device to generate intelligent, proactive responses to a read command. For example, signal and noise characteristics of a group of memory cells in a memory device are measured to determine a read voltage. An action is identified based on evaluation of the quality of data retrievable using the read voltage from the group of memory cells. While a response indicating the action is provided responsive to the command, the memory device can initiate the action proactively before a subsequent command, following the response, is received.
    Type: Grant
    Filed: May 7, 2020
    Date of Patent: August 3, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Sivagnanam Parthasarathy, James Fitzpatrick, Patrick Robert Khayat, AbdelHakim S. Alhussien
  • Semiconductor devices and semiconductor systems
    Patent number: 11062750
    Abstract: A semiconductor device includes a phase control signal generation circuit, a phase detection circuit, and a selection/transmission circuit. The phase control signal generation circuit outputs one of a command-shifted signal generated from a command/address signal and a clock-shifted signal generated from a clock signal as a phase control signal, based on a leveling enablement signal. The phase detection circuit detects a phase of a leveling clock signal in synchronization with the phase control signal to generate a detection signal. The selection/transmission circuit outputs the detection signal as one of a phase detection signal and a phase adjustment signal based on the leveling enablement signal.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Yoo Jong Lee, Kang Sub Kwak
  • Data output method and semiconductor device using the data output method
    Patent number: 11062749
    Abstract: A semiconductor device includes a read control circuit configured to generate first and second output control signals including pulses which are selectively generated, from first and second strobe signals depending on burst information; and a data output circuit configured to latch first internal data depending on the pulse of the first output control signal, transfer second internal data at a time when the second output control signal level-transitions, and generate output data from the latched first internal data and the transferred second internal data.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: July 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Kwang Hun Lee, Sang Sic Yoon
  • Nonvolatile memory devices, systems and methods with switching charge pump architectures
    Patent number: 11056155
    Abstract: A memory device can include a plurality of banks, each bank including a memory cell array of nonvolatile (NV) memory cells; a plurality of charge pumps, including a first charge pump and second charge pump; and a switch circuit. The switch circuit can be configured to, in a first mode, connect the first charge pump to first circuits of the banks and isolate the second charge pump from the first circuits, and in a second mode, isolate the first charge pump from the first circuits and connect the second charge pump to the first circuits.
    Type: Grant
    Filed: June 20, 2019
    Date of Patent: July 6, 2021
    Assignee: Adesto Technologies Corporation
    Inventors: Stephen Trinh, Duong Vinh Hao, Nguyen Khac Hieu, Hendrik Hartono, John Dinh, Shane Charles Hollmer
  • Memory device and method of operating the same
    Patent number: 11056162
    Abstract: Provided herein is a memory device and a method of operating the same. The memory device may include a memory cell array including a plurality of memory cells, page buffers coupled to the memory cell array through respective bit lines and a control logic configured to control so that, during a read operation, data stored in the memory cell array is sensed and stored in the page buffers, and the data stored in the page buffers is output to an external device, wherein the control logic controls a time point at which a discharge operation is to be performed after the sensing of the data, and a time point at which a data transfer operation between latches included in each of the page buffers is to be performed, in response to a read command received from the external device.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: July 6, 2021
    Assignee: SK hynix Inc.
    Inventors: Mi Sun Yoon, Dong Hyuk Chae
  • On chip block repair scheme
    Patent number: 11049585
    Abstract: Field configurable bad block repair for a memory array comprising a plurality of blocks utilizes a block repair information store for data identifying one or more bad blocks in the array. The block repair information store includes nonvolatile memory writable at least once. Block repair circuitry on the device is configurable to redirect commands to access bad blocks identified in the bad block repair information store to reserved blocks in the memory array. A controller is responsive to a command to write bad block repair information, such as an identifier of a bad block in the plurality of blocks to the block repair information store in the field, and to reconfigure the block repair circuitry in the field using the updated information.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 29, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shuo-Nan Hung, Chun-Hsiung Hung
  • Memory device and method of operating the memory device
    Patent number: 11049535
    Abstract: A page buffer includes a bit line sensing circuit, a latch, and a main latch for sensing and storing data from a memory cell. The bit line sensing circuit is coupled with the memory cell by a bit line and configured to perform a bit line sensing operation of sensing first data stored in the memory cell. The latch control circuit is coupled with the bit line sensing circuit. The main latch is coupled with the bit line sensing circuit through the latch control circuit and configured to perform a main latch operation of storing the sensed first data. The cache latch is coupled with the main latch and configured to perform a cache latch operation of storing second data stored in the main latch. Wherein a period of time of the cache latch operation overlaps with a period of time of the bit line sensing operation.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: June 29, 2021
    Assignee: SK hynix Inc.
    Inventor: Chul Woo Yang
  • Memory device having variable impedance memory cells and time-to-transition sensing of data stored therein
    Patent number: 11049553
    Abstract: The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 29, 2021
    Assignee: R&D 3 LLC
    Inventor: Ravindraraj Ramaraju
  • Column control circuit and semiconductor device including the same
    Patent number: 11049534
    Abstract: A column control circuit may include a column control signal generation circuit and a column access block signal generation circuit. The column control signal generation circuit is configured to activate an input/output strobe signal when a column access block signal is deactivated. The column control signal generation circuit is configured to deactivate the input/output strobe signal when the column access block signal is activated. The column access block signal generation circuit is configured to activate the column access block signal when gap-less read commands may be inputted. The column access block signal generation circuit may deactivate the column access block signal during a period corresponding to an N-th read command among the gap-less read commands. N is an integer that is no less than 2.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: June 29, 2021
    Assignee: SK hynix Inc.
    Inventors: Kyung Ho Chu, Soo Bin Lim, Yong Suk Joo
  • Magnetoresistive random access memory (MRAM) with OTP cells
    Patent number: 11049539
    Abstract: A magnetoresistive random access memory (MRAM) array has a corresponding MRAM cell, including a Magnetic Tunnel Junction (MTJ), at an intersection of each row and column. A first row of the array is configured as a single one-time-programmable (OTP) row, wherein a first MRAM cell in a first column is connected to a second MRAM cell in a second column. A first MTJ of the first MRAM cell is connected to a first bit line of the first column, and a second MTJ of the second MRAM cell is not connected to a second bit line of the second column. During a write to the first MRAM cell, write circuitry is configured to connect the first and second bit lines and the corresponding source lines such that the select transistors in the first and second MRAM cells are connected in parallel to drive a write current through the first MTJ.
    Type: Grant
    Filed: April 29, 2020
    Date of Patent: June 29, 2021
    Assignee: NXP USA, Inc.
    Inventors: Padmaraj Sanjeevarao, Jon Scott Choy, Anirban Roy
  • Multi-tier 3D memory and erase method thereof
    Patent number: 11037632
    Abstract: Provided is an erase method for a multi-tier three-dimension (3D) memory including a plurality of tiers and a plurality of blocks, each of the tiers including a plurality of word lines. The erase method includes: in erasing a selected block among the plurality of blocks, in a current iteration, selecting at least one tier among the plurality of tiers to be erased by a first erase voltage; determining whether the at least one tier passes erase verification; and if the at least one tier passes erase verification, in a next iteration, inhibiting the at least tier which already passes erase verification from erase.
    Type: Grant
    Filed: March 25, 2020
    Date of Patent: June 15, 2021
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventors: Shaw-Hung Ku, Chih-Chieh Cheng, Cheng-Hsien Cheng, Yu-Hung Huang, Atsuhiro Suzuki, Wen-Jer Tsai
  • Dual port SRAM cell with dummy transistors
    Patent number: 11031074
    Abstract: A semiconductor device includes a semiconductor substrate including a fin of semiconductor material having a fin width and a fin length. The fin length is greater than the fin width and extends between a first fin end and a second fin end. A gate electrode extends over the fin at a first fin location between the first fin end and the second fin end. A dummy gate electrode extends over the first fin end and is floating.
    Type: Grant
    Filed: April 30, 2020
    Date of Patent: June 8, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Jhon Jhy Liaw
  • Derivative receiver
    Patent number: 11031053
    Abstract: A derivative receiver includes a differentiator configured to differentiate an input signal; a comparator configured to produce a comparison signal by comparing a derivative signal produced using an output from the differentiator with a threshold voltage; and a pattern detecting equalizer configured to output a data signal by sampling an equalization signal generated by adjusting a level of the comparison signal. The level of the comparison signal is adjusted according to a past value of the data signal.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: June 8, 2021
    Assignees: SK hynix Inc., Seoul National University R&DB Foundation
    Inventors: Sungphil Choi, Suhwan Kim
  • Semiconductor memory device
    Patent number: 11024386
    Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell; a second memory cell; a first word line; a second word line; and a first bit line. The device is configured to execute a first operation, a second operation, and a third operation to write data into the first memory cell. In the first operation, a first voltage is applied to the second word line. In the second operation, after the first operation, a second voltage higher than the first voltage is applied to the second word line. In the third operation, after the second operation, a third voltage higher than the second voltage is applied to the first word line, and a fourth voltage lower than both the second voltage and the third voltage is applied to the second word line.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: June 1, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Masanobu Shirakawa, Takuya Futatsuyama
  • Memory system and operation method thereof
    Patent number: 11024402
    Abstract: A memory system may include: an error correction code (ECC) generation circuit suitable for generating an M-bit error correction code using N-bit data, where N and M are positive integers; a memory core suitable for storing the N-bit data and the M-bit error correction code; and an ECC circuit suitable for correcting an error of the N-bit data read from the memory core, using the M-bit error correction code read from the memory core, wherein the ECC generation circuit generates the M-bit error correction code using an M×(N+M) check matrix, wherein one column vector among M column vectors corresponding to the M-bit error correction code in the M×(N+M) check matrix has an odd weight, and the other M column vectors have even weights.
    Type: Grant
    Filed: April 8, 2020
    Date of Patent: June 1, 2021
    Assignee: SK hynix Inc.
    Inventor: Hoiju Chung
  • Compute-in-memory dynamic random access memory
    Patent number: 11011216
    Abstract: A compute-in-memory dynamic random access memory bitcell is provided that includes a first transistor having an on/off state controlled by a weight bit stored across a capacitor. The first transistor is in series with a current-source transistor connected between the first transistor and a read bit line. An activation voltage controls whether the current-source transistor conducts a current when the first transistor is in the on state.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: May 18, 2021
    Assignee: Qualcomm Incorporated
    Inventor: Ankit Srivastava
  • Retention voltage generator circuit
    Patent number: 11004482
    Abstract: Memory circuits used in computer systems may have different operating modes. In a retention mode, a voltage level of an array power supply node coupled to memory cells included in the memory circuit is reduced to a level sufficient to retain data, but not to perform read and write operations to the memory cells. A power converter circuit may be configured to generate the retention voltage level, and adjust the retention voltage level using a leakage current of dummy memory cells included in the memory circuit.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: May 11, 2021
    Assignee: Apple Inc.
    Inventors: Jaemyung Lim, Jiangyi Li, Mohamed H. Abu-Rahma, Shahzad Nazar, Jaroslav Raszka
  • Device including memory controller, memory device, and power management circuit, and method of operating the same
    Patent number: 11004529
    Abstract: The present technology includes a memory controller that controls auxiliary power cells of which the charge counts is small to be preferentially charged, based on charge count information of each of a plurality of auxiliary power cells included in an auxiliary power device that supplies power to a memory device and a memory controller.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: May 11, 2021
    Assignee: SK hynix Inc.
    Inventors: Yong Jin, Yoon Jin Kim, Joong Hyun An
  • Semiconductor memory device
    Patent number: 10998337
    Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. A second word line is provided above a first word line on a substrate. A third word line is provided above the second word line. A semiconductor layer includes a first part that passes through the first word line, a second part that passes through the second and the third word lines, and is provided above the first part, and a joint provided between the first and second parts. When a write operation is performed on a memory cell of the third word line, prior to applying a write voltage to the third word line, a first voltage is applied to a bit line, a second voltage is applied to the third word line, and a third voltage higher than the second voltage is applied to the second word line.
    Type: Grant
    Filed: August 13, 2020
    Date of Patent: May 4, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Kota Nishikawa, Hiroshi Tsubouchi, Kenri Nakai
  • Deterministic read disturb counter-based data checking for NAND flash
    Patent number: 10996870
    Abstract: A data storage device comprises a non-volatile semiconductor memory device and a solid-state drive controller communicatively coupled to the non-volatile semiconductor memory device. The non-volatile semiconductor memory device can store data in memory blocks. The solid-state drive controller can, periodically, retrieve counts from a counter table, select a predetermined number of memory blocks corresponding to the lowest counts, and determine an integrity of the stored data in each of the predetermined number of memory blocks. Each count can correspond to a difference between a count limit and a number of read operations performed on one of the memory blocks.
    Type: Grant
    Filed: March 6, 2020
    Date of Patent: May 4, 2021
    Assignee: Toshiba Memory Corporation
    Inventor: Neil Buxton