Patents Examined by Xiaoliang Chen
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Patent number: 11057992Abstract: A method for manufacturing connection structure, the method includes arranging conductive particles and a first composite on a first electrode located on a first surface of a first member, arranging a second composite on a region other than the first electrode of the first surface, arranging the first surface and a second surface of a second member where a second electrode is located, so that the first electrode and the second electrode are opposed to each other, pressing the first member and the second member; and curing the first composite and the second composite.Type: GrantFiled: December 19, 2019Date of Patent: July 6, 2021Assignee: MIKUNI ELECTRON CORPORATIONInventor: Sakae Tanaka
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Patent number: 11044817Abstract: A thermally conductive board comprises a metal substrate, a foil containing copper, a thermally conductive and insulating layer and a barrier layer. The thermally conductive and electrically insulating layer is disposed on the metal substrate. The barrier layer is laminated between the foil containing copper and the thermally conductive and electrically insulating layer. The barrier is in direct contact with the foil containing copper, and the interface between the barrier layer and the foil containing copper comprises a microrough surface. The barrier layer has a Redox potential between 0 and ?1V. The microrough surface has a roughness Rz of 2-18 ?m.Type: GrantFiled: April 9, 2020Date of Patent: June 22, 2021Assignee: POLYTRONICS TECHNOLOGY CORP.Inventors: Kuo-Hsun Chen, Chia-Hsiung Wu, Kai-Wei Lo, Yu-Hsuan Tseng
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Patent number: 11044808Abstract: A printed circuit board includes a core layer, a plurality of conductive pattern layers disposed on one side and the other side of the core layer, a plurality of insulating layers disposed on the one side and the other side of the core layer, and a plurality of via layers disposed on the one side and the other side of the core layer. The printed circuit board has a wiring region and a dummy region surrounding at least a portion outside of the wiring region on a plane. A metal ratio in the dummy region on one side and a metal ratio in the dummy region on the other side are different from each other.Type: GrantFiled: January 7, 2020Date of Patent: June 22, 2021Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Min Hee Yoon, Jong Eun Park, Sun Young Choi
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Patent number: 11044809Abstract: A flexible circuit board, a display panel and a display module are provided. The flexible circuit board includes a substrate layer and a colloid layer. The substrate layer has a lamination area and a non-lamination area, the lamination area is used to laminate and connect the flexible circuit board with the display panel, and the lamination area includes a guiding structure. The colloid layer is disposed on a side surface of the substrate layer including the guiding structure, and the guiding structure is used to guide a flow direction of a colloid in the colloid layer when the colloid layer is melted by heat.Type: GrantFiled: November 5, 2018Date of Patent: June 22, 2021Assignee: Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd.Inventor: Cui Huang
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Patent number: 11039530Abstract: Disclosed herein are communication devices and connected clothing systems. The communication devices comprise a circuit printed on a portion of fabric, the circuit comprising means for transmitting electrical signals to and from a user, a controller electrically pairable to the circuit, and means for attaching the circuit to an item of apparel. Connected clothing systems comprises a communication device as disclosed herein attached to an item of apparel.Type: GrantFiled: June 21, 2019Date of Patent: June 15, 2021Assignee: TARO06 LLCInventor: Kikka Hanazawa
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Patent number: 11027856Abstract: Multifunctional surfacing materials for use in composite structures are disclosed. According to one embodiment, the surfacing material includes (a) a stiffening layer, (b) a curable resin layer, (c) a conductive layer, and (d) a nonwoven layer, wherein the stiffening layer (a) and the nonwoven layer (d) are outermost layers, and the exposed surfaces of the outermost layers are substantially tack-free at room temperature (20° C. to 25° C.). The conductive layer may be interposed between the curable resin layer and the stiffening layer or embedded in the curable resin layer. According to another embodiment, the surfacing material includes a fluid barrier film between two curable resin layers. The surfacing materials may be in the form of a continuous or elongated tape that is suitable for automated placement.Type: GrantFiled: November 29, 2016Date of Patent: June 8, 2021Assignee: CYTEC INDUSTRIES INC.Inventors: Junjie Jeffrey Sang, Dalip Kumar Kohli, Kevin R. Mullery
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Patent number: 11032901Abstract: Provided is a printed circuit board including: a first flexible insulating layer; a first rigid insulating layer stacked on a first portion of the first flexible insulating layer; and an electronic element embedded in the first flexible insulating layer in stacked formation with the rigid insulating layer.Type: GrantFiled: October 24, 2019Date of Patent: June 8, 2021Assignee: Samsung Electro-Mechanics Co., Ltd.Inventor: Jung-Hwan Park
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Patent number: 11032915Abstract: A single-layer circuit board, multi-layer circuit board, and manufacturing methods therefor. The method for manufacturing the single-layer circuit board comprises the following steps: drilling a hole on a substrate, the hole comprising a blind hole and/or a through hole; on a surface of the substrate, forming a photoresist layer having a circuit negative image; forming a conductive seed layer on the surface of the substrate and a hole wall of the hole; removing the photoresist layer, and forming a circuit pattern on the surface of the substrate, wherein forming a conductive seed layer comprises implanting a conductive material below the surface of the substrate and below the hole wall of the hole via ion implantation, and forming an ion implantation layer as at least part of the conductive seed layer.Type: GrantFiled: June 25, 2020Date of Patent: June 8, 2021Assignee: RICHVIEW ELECTRONICS CO., LTD.Inventors: Siping Bai, Xianglan Wu, Zhijian Wang, Zhigang Yang, Jinqiang Zhang
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Patent number: 11026326Abstract: A printed circuit board (PCB) structure and mounting assembly for joining two PCBs. A first PCB has a top and bottom surface faces and a peripheral end face separating the top and bottom surface. The first PCB has one or more conductive wire ends exposed at a surface of the peripheral end face; the exposed conductive wire ends forming multiple separate electrical contacts across the thickness and length of the PEF surface. A second PCB has a top surface face and one or more conductive pads exposed at the top surface at locations corresponding to locations of the multiple electrical contacts. A surface mount solder material is disposed on one or more exposed conductive pads for electrically connecting with corresponding the multiple electrical contacts. The disposed solder material stably joins the PEF surface of the first PCB to the top surface of the second PCB in a relative perpendicular orientation.Type: GrantFiled: August 1, 2019Date of Patent: June 1, 2021Assignee: International Business Machines CorporationInventors: Todd E. Takken, Xin Zhang, Yuan Yao, Andrew Ferencz
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Patent number: 11018452Abstract: A positioning fastener includes a base having a seat plate extended therefrom, a fixing portion disposed below the base for fastening to an electronic substrate, and an elastic positioning structure disposed above the base and including an urging plate, a pressing plate connected to the urging plate, a positioning space defined therein and a positioning member disposed at a bottom side thereof. The urging plate and the pressing plate are squeezed backwards and elastically deformed by a circuit board that is rotated downward so that the circuit board passes the urging plate and moves into the positioning space of the elastic positioning structure and a suspended board edge of the circuit board is secured in position by the positioning member. The pressing plate can be pressed by an external force to lift the urging plate, allowing the circuit board to be rotated in direction away from the positioning member.Type: GrantFiled: September 24, 2019Date of Patent: May 25, 2021Assignee: HANWIT PRECISION INDUSTRIES LTD.Inventors: Ming-De Wu, Ching-Kai Chang
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Patent number: 11013116Abstract: A flexible assembly for a display device and the display device are provided. The flexible assembly includes a flexible substrate, and a first output pad, a second output pad, a third output pad and a fourth output pad that are arranged on the substrate. The first output pad, the second output pad, the third output pad and the fourth output pad are sequentially arranged along a first direction and are spaced apart from each other. A pitch is between each output pad and an adjacent output pad, and the pitch is a sum of a spacing distance between each output pad and the adjacent output pad and a width of the adjacent output pad in the first direction. The pitch between the first output pad and the adjacent second output pad is smaller than the pitch between the third output pad and the adjacent fourth output pad.Type: GrantFiled: March 27, 2019Date of Patent: May 18, 2021Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Liqiang Chen, Paoming Tsai, Weifeng Zhou, Chen Xu, Jifeng Tan
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Patent number: 11013109Abstract: A display unit includes a display panel, a circuit board bent from a front surface of the display panel toward a rear surface of the display panel, a window disposed on the front surface of the display panel to cover an active area, and a cover panel film disposed on the rear surface of the display panel and disposed between the display panel and the circuit board. The cover panel film includes a first portion overlapping with the display panel, and a second portion extending from the first portion to protrude from the display panel when viewed in a plan view. The second portion is disposed between the circuit board and the window when viewed in a cross-sectional view.Type: GrantFiled: October 15, 2019Date of Patent: May 18, 2021Assignee: Samsung Display Co., Ltd.Inventors: Jung-Soo Han, Hwa-Su Lim
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Patent number: 11013130Abstract: A display device includes a display panel including a display area on which a plurality of display elements is disposed and a non-display area on which one or more wires for driving the plurality of display elements are disposed. A back cover is attached to one surface of the display panel and has a plurality of openings. A roller unit winds or unwinds the back cover and the display panel, and a lifting unit moves the back cover and the display panel in a vertical direction. The plurality of openings overlaps the display panel, and each of the plurality of openings is disposed to be staggered with one or more of the openings in an adjacent row. A size of the back cover is larger than a size of the display panel.Type: GrantFiled: June 27, 2019Date of Patent: May 18, 2021Assignee: LG Display Co., Ltd.Inventors: Mi-Na Shin, ChounSung Kang, SunBok Song, GeunChang Park, Moonsun Lee
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Patent number: 11006521Abstract: Provided are a wiring base plate and the like including an insulating substrate including a first surface portion including an aluminum oxide-based sintered body and a mullite-based sintered body; and a metallization layer including a second surface portion, the second surface portion containing at least one of a manganese compound and a molybdenum compound and being in contact with the first surface portion of the insulating substrate; wherein the second surface portion of the metallization layer and the first surface portion of the insulating substrate contain at least one of a manganese silicate phase and a magnesium silicate phase.Type: GrantFiled: January 24, 2018Date of Patent: May 11, 2021Assignee: KYOCERA CorporationInventors: Isamu Kirikihira, Makoto Yamamoto
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Patent number: 11006527Abstract: An aspect includes one or more board layers. A first chip cavity is formed within the one or more board layers, wherein a first Josephson amplifier or Josephson mixer is disposed within the first chip cavity. The first Josephson amplifier or Josephson mixer comprises at least one port, each port connected to at least one connector disposed on at least one of the one or more board layers, wherein at least one of the one or more board layers comprises a circuit trace formed on the at least one of the one or more board layers.Type: GrantFiled: July 15, 2019Date of Patent: May 11, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Baleegh Abdo, Nicholas T. Bronn, Oblesh Jinka, Salvatore B. Olivadese
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Patent number: 10999929Abstract: The present disclosure describes expansion card interfaces for a printed circuit board and methods of making the same. The methods include forming electrical pads of the expansion card interface on a substrate, and dividing at least one electrical pad into a first portion and a second portion. The resulting expansion card interfaces have the first portion conductively coupled to a circuit on the printed circuit board, and the second portion conductively isolated from the first portion.Type: GrantFiled: December 13, 2019Date of Patent: May 4, 2021Assignee: QUANTA COMPUTER INC.Inventors: Che-Wei Chang, Cheng-Hsien Lee
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Patent number: 10993314Abstract: A printed circuit board includes a plurality of layers including attachment layers and routing layers; and columns of via patterns formed in the plurality of layers, wherein via patterns in adjacent columns are offset in a direction of the columns, each of the via patterns comprising: first and second signal vias forming a differential signal pair, the first and second signal vias extending through at least the attachment layers; and at least one conductive shadow via located between the first and second signal vias of the differential pair. In some embodiments, at least one conductive shadow via is electrically connected to a conductive surface film.Type: GrantFiled: October 29, 2019Date of Patent: April 27, 2021Assignee: Amphenol CorporationInventors: Marc Robert Charbonneau, Jose Ricardo Paniagua
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Patent number: 10984957Abstract: A capacitor comprises a housing and a first stack of parallel plates within the housing. A first plate and a second plate in the first stack are capacitively coupled. The capacitor comprises a second stack of parallel plates within the housing. A third plate and a fourth plate in the stack are capacitively coupled. The capacitor also comprises a first input electrode and a second input electrode. The capacitor also comprises a first output electrode and a second output electrode on a side surface of the capacitor. The capacitor also comprises a dielectric material located between each plate in the first stack and the second stack. The first stack is not capacitively coupled with the second stack.Type: GrantFiled: December 3, 2019Date of Patent: April 20, 2021Assignee: International Business Machines CorporationInventors: Samuel R. Connor, Stuart Brett Benefield, Matthew Doyle
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Patent number: 10980127Abstract: A method is provided for forming a printed circuit board (PCB) assembly. The method may include drilling a first plurality of vias having a first diameter in a PCB and filling the first plurality of vias to form a first plurality of plated or filled vias. The method may also include drilling a second plurality of vias having a second diameter in the PCB, and filling the second plurality of vias to form a second plurality of plated or filled vias. The first plurality of plated or filled vias is mixed with the second plurality of plated or filled vias such that the spacing between the first plurality of plated or filled vias and the second plurality of plated or filled vias is less than the first diameter and the second diameter.Type: GrantFiled: June 7, 2019Date of Patent: April 13, 2021Assignee: TTM Technologies Inc.Inventors: Michael Len, Chong Mei, Michael Lugert, Raj Kumar
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Patent number: 10980129Abstract: An asymmetric electronic substrate and method of making the substrate includes forming a first layer on each opposing major surface of a removable carrier layer, the first layer being a routing layer, simultaneously laminating the first layers, and building up subsequent layers on layers previously formed and laminated on the removable carrier layer iteratively. The subsequent layers including routing layers and a core layer formed on each side of the removable carrier layer, the core layer including through holes having a larger gauge than through holes included in the routing layers. A number of layers on a first side of the core layer, between the core layer and the carrier layer, is different than a number of layers on a second side of the core layer. The carrier layer is removed to produce two asymmetric substrates, each asymmetric substrate including one of the at least one core layers.Type: GrantFiled: March 16, 2020Date of Patent: April 13, 2021Assignee: Intel CorporationInventors: Sri Chaitra Jyotsna Chavali, Amruthavalli Pallavi Alur, Wei-Lun Kane Jen, Sriram Srinivasan