Patents Examined by Yaima Campos
  • Patent number: 8578105
    Abstract: Various technologies and techniques are disclosed for providing type stability techniques to enhance contention management. A reference counting mechanism is provided that enables transactions to safely examine states of other transactions. Contention management is facilitated using the reference counting mechanism. When a conflict is detected between two transactions, owning transaction information is obtained. A reference count of the owning transaction is incremented. The system ensures that the correct transaction was incremented. If the owning transaction is still a conflicting transaction, then a contention management decision is made to determine proper resolution. When the decision is made, the reference count on the owning transaction is decremented by the conflicting transaction. When each transaction completes, the reference counts it holds to itself is decremented. Data structures cannot be deallocated until their reference count is zero.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: November 5, 2013
    Assignee: Microsoft Corporation
    Inventors: David Detlefs, Michael M. Magruder, John Joseph Duffy
  • Patent number: 8566537
    Abstract: A method and apparatus to facilitate shared pointers in a heterogeneous platform. In one embodiment of the invention, the heterogeneous or non-homogeneous platform includes, but is not limited to, a central processing core or unit, a graphics processing core or unit, a digital signal processor, an interface module, and any other form of processing cores. The heterogeneous platform has logic to facilitate sharing of pointers to a location of a memory shared by the CPU and the GPU. By sharing pointers in the heterogeneous platform, the data or information sharing between different cores in the heterogeneous platform can be simplified.
    Type: Grant
    Filed: March 29, 2011
    Date of Patent: October 22, 2013
    Assignee: Intel Corporation
    Inventors: Yang Ni, Rajkishore Barik, Ali-Reza Adl-Tabatabai, Tatiana Shpeisman, Jayanth N. Rao, Ben J. Ashbaugh, Tomasz Janczak
  • Patent number: 8549240
    Abstract: Disclosed is a data recovery mechanism associated with a data writing process in a storage area network (SAN). In general, a data writing mechanism is provided so that a particular host can write data to a storage device in a particular SAN session. One specific example of a data writing mechanism is a data tapping mechanism that provides a copy of this data to an appliance. The data recovery mechanism allows the appliance to recover data from the particular target, for example, when the data was unsuccessfully mirrored to the appliance during the data tapping or when the appliance needs to obtain the data that was written prior to a data tapping procedure being initiated. In one embodiment, the data recovery mechanism is set up so that the appliance can recover data from the target by mimicking the particular host.
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: October 1, 2013
    Assignee: Cisco Technology, Inc.
    Inventors: Samar Sharma, Roy M. D'Cruz, Sanjaya Kumar, Jhaanaki M. Krishnan
  • Patent number: 8549252
    Abstract: A file-mapped volume is a logical volume in which the data storage of the logical volume is the data storage of a regular file associated with the logical volume. The regular file can be a file of a first file system, and a second file system can be built upon the file-mapped volume. These two file systems can have distinct inode address spaces, yet files of the first file system are easily moved to the second file system by changing pointers to inodes of these files. The second file system can be easily copied, attached, or transported by copying, attaching, or transporting the regular file containing the second file system, yet files in the second file system can be accessed in real time via file access routines of the operating system.
    Type: Grant
    Filed: December 13, 2005
    Date of Patent: October 1, 2013
    Assignee: EMC Corporation
    Inventor: Virendra M. Mane
  • Patent number: 8527720
    Abstract: A method for pre-staging data includes obtaining a DST configuration of a virtual volume at a first point in time. The method also includes creating a Point-in-Time copy (PiT) in a destination storage pool when the virtual volume includes at least one PiT, or reconfiguring at least one virtual volume segment to contain a hot-spot. The virtual volume may or may not have PiTs. The method further includes recording the DST configuration, specifying the DST configuration be applied to the storage array at a second point in time, and applying the DST configuration to the storage array at the second point in time.
    Type: Grant
    Filed: December 3, 2008
    Date of Patent: September 3, 2013
    Assignee: LSI Corporation
    Inventor: Martin Jess
  • Patent number: 8504773
    Abstract: A system and method for buffering intermediate data in a processing pipeline architecture stores the intermediate data in a shared cache that is coupled between one or more pipeline processing units and an external memory. The shared cache provides storage that is used by multiple pipeline processing units. The storage capacity of the shared cache is dynamically allocated to the different pipeline processing units as needed, to avoid stalling the upstream units, thereby improving overall system throughput.
    Type: Grant
    Filed: December 2, 2008
    Date of Patent: August 6, 2013
    Assignee: Nvidia Corporation
    Inventors: David B. Glasco, Peter B. Holmqvist, George R. Lynch, Patrick R. Marchand, James Roberts
  • Patent number: 8484438
    Abstract: Some embodiments provide a system that facilitates concurrency control in a computer system. During operation, the system generates a set of signatures associated with memory accesses in the computer system. To generate the signatures, the system creates a set of hierarchical Bloom filters (HBFs) corresponding to the signatures, and populates the HBFs using addresses associated with the memory accesses. Next, the system compares the HBFs to detect a potential conflict associated with the memory accesses. Finally, the system manages concurrent execution in the computer system based on the detected potential conflict.
    Type: Grant
    Filed: June 29, 2009
    Date of Patent: July 9, 2013
    Assignee: Oracle America, Inc.
    Inventor: Robert E. Cypher
  • Patent number: 8468295
    Abstract: Systems and methods for reducing problems and disadvantages associated with power consumption in memory devices are disclosed. A method for reducing power consumption in memory may include tracking, by an operating system executing on a processor, one or more logical units of a memory system that are in use. The method may also include setting, by the operating system, a variable indicating a portion of the memory system in use based on the logical units of the memory system in use. The method may additionally include refreshing one or more of the one or more logical units of the memory system based on the variable.
    Type: Grant
    Filed: December 2, 2009
    Date of Patent: June 18, 2013
    Assignee: Dell Products L.P.
    Inventors: Stuart Allen Berke, William Sauber
  • Patent number: 8464013
    Abstract: A method and apparatus for constructing a memory-based database service platform, in which database can be on-loaded and off-loaded or unloaded as needed, and can reserve schedule and size of memory and other resources, including CPUs, network, backup, mirroring and recovery recourses. With the service platform, multiple different types of databases can be chosen by specifying data storage type and data operation interfaces, such as Relational Database (RDB), Biometric Database (BDB), Time Series Database (TDB), Data Driven Database (DDDB) and File-based Database (FDB) etc. Database types can be chosen either by user directly or by platform automatically or semi-automatically based on data types and data operation characteristics.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: June 11, 2013
    Assignee: Intelitrac Inc.
    Inventor: Tianlong Chen
  • Patent number: 8458426
    Abstract: In a transceiver system a first interface receives data from a first channel using a first clock signal and transmits data to the first channel using a second clock signal. A second interface receives data from a second channel using a third clock signal and transmits data to the second channel using a fourth clock signal. A re-timer re-times data received from the first channel using the first clock signal and retransmits the data to the second channel using the fourth clock signal.
    Type: Grant
    Filed: January 19, 2007
    Date of Patent: June 4, 2013
    Assignee: Rambus Inc.
    Inventors: Kevin Donnelly, Mark Johnson, Chanh Tran, Nancy D. Dillon
  • Patent number: 8458419
    Abstract: Systems and methods for backing up applications executing on a virtual machine are provided. The method comprises submitting a first notification to a remote computing system to prepare an application running on a virtual machine for backup, such that application data consistency is maintained during the backup process; receiving a second notification from the remote computing system, indicating that the application is prepared for backup; creating a snapshot of the virtual machine in response to the second notification; and receiving application data from the computing system to process the snapshot and complete an application-specific backup for the virtual machine.
    Type: Grant
    Filed: February 27, 2008
    Date of Patent: June 4, 2013
    Assignee: International Business Machines Corporation
    Inventors: Jason Ferris Basler, David George Derk, James Patrick Smith
  • Patent number: 8447916
    Abstract: Aspects of the subject matter described herein relate to storage configuration. In aspects, an interface is used to discover the existence, capacity, and characteristics of solid state storage. This information may be provided to a user or storage management process which may use the information to configure the solid state storage. When appropriate, bus bandwidth to the solid state storage as well as bandwidth to memory components of the solid state storage may be configured. Configuration and re-configuration may be performed automatically according to one or more policies maintained locally or remotely.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: May 21, 2013
    Assignee: Microsoft Corporation
    Inventors: Trenton P. Rambo, Sean Nicholas McGrane
  • Patent number: 8447949
    Abstract: One or more registers used to form an address usable in accessing storage are examined to determine if a zero address event has occurred in forming the address. In response to an indication that a zero address event has occurred in address formation, an alert is provided to the program using the address to access storage.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: May 21, 2013
    Assignee: International Business Machines Corporation
    Inventors: Robert M. Abrams, Mark S. Farrell, Dan F. Greiner, Christian Jacobi, James H. Mulder, Peter J. Relson, Timothy J. Slegel, Peter K. Szwed
  • Patent number: 8443137
    Abstract: The is provided a storage system comprising a plurality of disk units adapted to store data at respective ranges of logical block addresses (LBAs), said addresses constituting an entire address space, and a storage control grid operatively connected to the plurality of disk units and comprising a plurality of data servers.
    Type: Grant
    Filed: February 11, 2010
    Date of Patent: May 14, 2013
    Assignee: Infinidat Ltd.
    Inventors: Yechiel Yochai, Leo Corry, Haim Kopylovitz
  • Patent number: 8443131
    Abstract: Operational information read out by a read-out sense amplifier (19) is transferred via the data line DB to a volatile memory section. The volatile memory section is configured with the volatile memory section (21) having a SRAM configuration and the second volatile memory section (23) configured with latch circuits, both sections respectively connected in parallel with the data line DB. The operational information, which may be provided depending on an operation state of the write-protect information and other information stored in the non-volatile memory cell MC selected by the word line WLWP, is written and read out with respect to the first volatile memory section (21) in response to the identification information linked with the operational information. The operational information which must be constantly accessible, is written into the second volatile memory section (23). Thus, the operational information is available in response to attributes of the operational information.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: May 14, 2013
    Assignee: Spansion LLC
    Inventors: Mitsuhiro Nagao, Kenta Kato
  • Patent number: 8438353
    Abstract: A method, system, and computer readable medium for asynchronously processing write operation on a volume having copy-on-write snapshots. In one embodiment, the method comprises the steps of: updating a normal mirror with write data associated with a write operation for the volume; asynchronously copying the write data from an asynchronous mirror to at least one copy-on-write snapshot; and, once the at least one copy-on-write snapshot is updated, updating the asynchronous mirror with the write data from the normal mirror.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: May 7, 2013
    Assignee: Symantec Operating Corporation
    Inventors: Prem Anand Ramanathan, Niranjan Sanjiv Pendharkar, Subhojit Roy
  • Patent number: 8438358
    Abstract: A system and method are provided for using a system-on-chip (SoC) memory speed control logic core to control memory maintenance and access parameters. A SoC is provided with an internal hardware-enabled memory speed control logic (MSCL) core. An array of SoC memory control parameter registers is accessed and a set of parameters is selected from one of the registers. The selected set of parameters is delivered to a SoC memory controller, to replace an initial set of parameters, and the memory controller manages an off-SoC memory using the delivered set of parameters.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: May 7, 2013
    Assignee: Applied Micro Circuits Corporation
    Inventors: Waseem Saify Kraipak, George Bendak
  • Patent number: 8433861
    Abstract: A method and apparatus for managing access to backup data on an archival storage system through storage media servers are described. In some examples, read operations are initiated. Each of the read operations is targeted to a respective plurality of the media servers specific for reading backup data from the archival storage system. Each read operation is delegated to each of its respective plurality of media servers until one of the respective plurality of media servers is available. The backup data specified by each read operation is read by the one media server of the respective plurality of media servers that is available. Each read operation may comprise a backup restoration, backup duplication, backup verification, or synthetic backup operation. Read operations can be targeted to a first and second plurality of media servers, which may be mutually exclusive. The archival storage system can be a tape storage system.
    Type: Grant
    Filed: September 25, 2008
    Date of Patent: April 30, 2013
    Assignee: Symantec Corporation
    Inventors: Thomas Schlender, Brian Boehm
  • Patent number: 8429378
    Abstract: A system and method to manage a translation lookaside buffer (TLB) is disclosed. In a particular embodiment, a method of managing a first TLB includes in response to starting execution of a memory instruction, setting a first field associated with an entry of the first TLB to indicate use of the entry. The method also includes setting a second field to indicate that the entry in the first TLB matches a corresponding entry in a second TLB.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: April 23, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Ajay Anant Ingle, Erich James Plondke, Muhammad T. Rab
  • Patent number: 8429374
    Abstract: System, method, and program to perform simultaneous read and write operations in a NAND-type memory device, including: assigning a first partition in a NAND-type memory device, wherein the first partition is configured to perform read operations on high priority read content; assigning a second partition in the NAND-type memory device, wherein the second partition is configured to perform read operations and write operations, wherein the read operations are performed on non-high priority read content; and controlling the first partition and second partition to operate in a simultaneous manner.
    Type: Grant
    Filed: March 22, 2010
    Date of Patent: April 23, 2013
    Assignees: Sony Corporation, Sony Mobile Communications AB
    Inventor: Wladyslaw Bolanowski