Abstract: A memory controller converts controller output signals output from a controller into memory input signals according to the operation specifications of memory chips to operate, and outputs the resultant to the memory chips through a common bus. The memory controller also receives memory output signals output from the memory chips through the common bus, and converts the received signals into controller input signals receivable to the controller. This allows the single memory controller to access the plurality of types of memory chips. As a result, the memory controller can be reduced in chip size, lowering the cost of the memory system.

Abstract: A first storage system is connected to a second storage system, and an external device within the first storage system is provided to a host as a device of the second storage system. The second storage system includes a cache control section having cache adaptors, each controlling a disk and a cache, a protocol conversion section including protocol adaptors that switch requests from the host to appropriate ones of the cache adaptors, a management adaptor, and an internal network that mutually connects the cache adaptors, the protocol adaptors and the management adaptor. The first storage system being connected to any of the protocol adaptors is connected to the second storage system. The second storage system executes a processing for the external device by the cache control section, or connects to the first storage system through the protocol conversion section without the cache control section executing processing for the external device.

Abstract: The invention relates to page fault handling in a virtualized computer system in which at least one guest page table maps virtual addresses to guest physical addresses, some of which are backed by machine addresses, and wherein at least one shadow page table and at least one translation look-aside buffer map the virtual addresses to the corresponding machine addresses. Indicators are maintained in entries of at least one shadow page table, wherein each indicator denotes a state of its associated entry from a group of states consisting of: a first state and a second state. An enhanced virtualization layer processes hardware page faults. States of shadow page table entries corresponding to hardware page faults are determined. Responsive to a shadow page table entry corresponding to a hardware page fault being in the first state, that page fault is delivered to a guest operating system for processing without activating a virtualization software component.

Abstract: At least one processor for executing a plurality of programs, a storage area which is capable of storing an information element temporarily, and a storage device which is capable of storing the information element, are provided. A certain level of importance is associated with each of the programs themselves or a performance requirement of each program. When a certain information element is output as a result of execution of a certain program from among the plurality of programs, the certain information element is written into the storage area. Then, a plurality of information elements written in the storage area is output to the storage device side in order of precedence from the information element of the executed program, or the performance requirement thereof, having the highest level of importance.

Abstract: A method for data integrity protection includes storing items of data in a plurality of data blocks in a storage medium. Respective block signatures are stored in an integrity structure in the storage medium. A block signature of the given data block is computed in response to a first request to read a first data item from a given data block, and the computed signature is verified against a stored signature read from the integrity structure. The verified block signature is saved in a secure cache. The block signature is recomputed upon receiving a second request to read a second data item, subsequent to the first request, and is verified against the verified block signature in the secure cache. The data item is output from the storage medium in response to verifying the recomputed block signature.

Abstract: There is provided is an interface apparatus including: a stream converter receiving write-addresses and write-data, storing the received data in a buffer, and sorting the stored write-data in the order of the write-addresses to output the write-data as stream-data; a cache memory storing received stream-data if a load-signal indicates that the stream-data are necessarily loaded and outputting data stored in a storage device corresponding to an input cache-address as cache-data; a controller determining whether or not data allocated with a read-address have already been loaded, outputting the load-signal instructing the loading on the cache memory if not loaded, and outputting a load-address indicating a load-completed-address of the cache memory; and at least one address converter calculating which one of the storage devices the allocated data are stored in, by using the load-address, outputting the calculated value as the cache-address to the cache memory, and outputting the cache-data as read-data.

Abstract: A system and method for servicing translation lookaside buffer (TLB) misses may manage separate input and output pipelines within a memory management unit. A pending request queue (PRQ) in the input pipeline may include an instruction-related portion storing entries for instruction TLB (ITLB) misses and a data-related portion storing entries for potential or actual data TLB (DTLB) misses. A DTLB PRQ entry may be allocated to each load/store instruction selected from the pick queue. The system may select an ITLB- or DTLB-related entry for servicing dependent on prior PRQ entry selection(s). A corresponding entry may be held in a translation table entry return queue (TTERQ) in the output pipeline until a matching address translation is received from system memory. PRQ and/or TTERQ entries may be deallocated when a corresponding TLB miss is serviced. PRQ and/or TTERQ entries associated with a thread may be deallocated in response to a thread flush.

Abstract: An apparatus for allocating entries in a set associative cache memory includes an array that provides a first pseudo-least-recently-used (PLRU) vector in response to a first allocation request from a first functional unit. The first PLRU vector specifies a first entry from a set of the cache memory specified by the first allocation request. The first vector is a tree of bits comprising a plurality of levels. Toggling logic receives the first vector and toggles predetermined bits thereof to generate a second PLRU vector in response to a second allocation request from a second functional unit generated concurrently with the first allocation request and specifying the same set of the cache memory specified by the first allocation request. The second vector specifies a second entry different from the first entry from the same set. The predetermined bits comprise bits of a predetermined one of the levels of the tree.

Abstract: A flash memory device includes a flash memory and a buffer memory. The flash memory is divided into a main region and a spare region. The buffer memory is a random access memory and has the same structure as the flash memory. In addition, the flash memory device further includes control means for mapping an address of the flash memory applied from a host so as to divide a structure of the buffer memory into a main region and a spare region and for controlling the flash memory and the buffer memory to store data of the buffer memory in the flash memory or to store data of the flash memory in the buffer memory.

Abstract: The storage system of the present invention is able to generate one virtual logical device from different logical devices which exist in each of the different storage control units and remote-copy all or part of the virtual logical device to another logical device. The same virtual identifier is set for a volume of the first storage unit and for a volume of the second storage unit. The path control unit of the host identifies a plurality of volumes which have the same virtual identifier as one virtual volume. A remote copy pair can also be set by a virtual volume and a volume of the third storage unit. The setting of the virtual volume and the setting of the remote copy can be performed by means of an instruction from the management server.

Abstract: A write-once optical disc and a method and apparatus for recording management information on the disc are provided. The method includes recording an opened SRR information on a recording medium, and removing an identification of a certain SRR from the opened SRR information once the certain SRR is closed. The opened SRR information carries an identification of any opened SRR, and the number of opened SRRs allowed is at most a predetermined number.

Abstract: Systems and methods for managing mapping information for objects maintained in a distributed storage system are provided. The distributed storage system can include a keymap subsystem that manages the mapping information according to object keys. Requests for specific object mapping information are directed to specific keymap coordinators within the keymap subsystem. Each keymap coordinator can maintain a cache for caching mapping information maintained at various information sources. To manage the cache, the keymap system can utilize information placeholders that replace previously cached keymap information while a request to modify keymap information is being processed by the information sources. Each keymap coordinator can process subsequently received keymap information read requests in the event an information placeholder is cached as the current cached keymap information.

Abstract: In response to a data request of a first processing unit among a plurality of processing units, the first processing unit selects a victim cache line to be castout from the lower level cache of the first processing unit and selects the lower level cache of a second of the plurality of processing units as an intended destination of a lateral castout (LCO) command by randomized round-robin selection. The first processing unit issues on the interconnect fabric an LCO command identifying the victim cache line and the intended destination. In response to a coherence response to the LCO command indicating success of the LCO command, the first processing unit removes the victim cache line from its lower level cache, and the victim cache line is held in the lower level cache of one of the plurality of processing units other than the first processing unit.

Abstract: The storage control apparatus arranges, in microprocessor packages, management information relating to logical volumes managed by the microprocessor packages. In a predetermined case, each of the management information is rearranged in appropriate places. The management information can be moved, taking into account the difference in the technical properties between a mainframe and an open system host.

Abstract: Multi-processor systems and methods are disclosed that employ a pre-fetch buffer to provide data fills to a source processor in response to a request. A pre-fetch buffer retrieves data as a uncached data fill. The source processor processes the data in response to a source request.

Abstract: The present invention aims to provide an apparatus capable of determining whether or not content is permitted to be taken out, by managing contents permitted to be taken out. One aspect of the invention is characterized by comprising: a storage means that stores therein taking-out-permitted-content identification data which is data generated on the basis of a part or entirety of each content permitted to be taken out; and a generating means that generates the taking-out-permitted-content identification data. Another aspect of the present invention is characterized by comprising: a storage means that stores therein taking-out-permitted-content identification data which is data generated on the basis of a part or entirety of each content permitted to be taken out to the outside; and an approving means that determines whether a content is permitted to be taken out, with reference to the taking-out-permitted-content identification data.

Abstract: In one embodiment of the present invention, a method and system are provided to control access to the non-volatile log (NVlog) of a storage server. By controlling access to the NVLog of a storage server the relative disk write bandwidth available to different client write requests can be controlled. The incoming write request can be categorized, and, during times of heavy load, only be permitted to use NVLog space as permitted based on the categorization of each write request. In one embodiment, the present invention includes receiving a write request from a client at a storage server, and determining whether the received write request can be presently logged in a NVlog based on a category of the write request.

Abstract: A design structure for a processor system may be embodied in a machine readable medium for designing, manufacturing or testing a processor integrated circuit. The design structure may embody a processor integrated circuit including multiple processors with respective processor cache memories. The design structure may specify enhanced cache coherency protocols to achieve cache memory integrity in a multi-processor environment. The design structure may describe a processor bus controller manages cache coherency bus interfaces to master devices and slave devices. The design structure may also describe a master I/O device controller and a slave I/O device controller that couple directly to the processor bus controller while system memory couples to the processor bus controller via a memory controller.

Abstract: From among a plurality of threads accessing a shared data object, one thread acquires a “master” status to arbitrate among the requests of competing threads during a given session of data access to the shared data object. During the session, the master thread resolves any conflicts resulting from attempts to access or modify the shared data object by other threads, and only the master thread may apply modifications to the shared data object during the session. Meanwhile, during the session, non-master threads may perform non-blocking read operations on the shared data object. During a subsequent session, a different thread may acquire master status.

Abstract: The present invention provides a memory management method, including the steps of: securing a memory area by a program executed by a computer; storing an object in the memory area in accordance with the execution of the program; bringing the memory area into a release reservation state in accordance with the program instructing the memory area to be released; moving the object to a memory area not to be released while another object in the memory area not to be released and not to be brought into the release reservation state refers to the object in the memory area to be released including the memory area to be brought into the release reservation state; and releasing the memory area to be released.