Patents Examined by Yaima Campos
  • Patent number: 8352672
    Abstract: A memory system includes a nonvolatile memory having a plurality of data blocks each of which is a unit of data erase and has a plurality of pages, each of the pages being a unit of data write, and a controller which checks whether or not the nonvolatile memory has been affected by power interruption at power-on time and, if the nonvolatile memory has been affected by power interruption, writes data to that first page in a first data block which has not been affected by power interruption.
    Type: Grant
    Filed: November 28, 2008
    Date of Patent: January 8, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Takaya Suda
  • Patent number: 8352690
    Abstract: Described embodiments provide a media controller that synchronizes data cached in a buffer and corresponding data stored in one or more sectors of a storage device. A buffer layer module of the media controller caches data transferred between the buffer and the storage device. One or more contiguous sectors are associated with one or more chunks. The buffer layer module updates a status corresponding to each chunk of the cached data and scans the status corresponding to a first chunk of cached data. If, based on the status, the first chunk of cached data is more recent than the corresponding data stored on the storage device, a media layer module synchronizes the data on the storage device with the cached data. The status corresponding to the group of one or more sectors is updated. The media layer module scans a next chunk of cached data, if present.
    Type: Grant
    Filed: March 24, 2010
    Date of Patent: January 8, 2013
    Assignee: LSI Corporation
    Inventors: Carl Forhan, Timothy Swatosh, Pamela Hempstead, Timothy Lund, Michael Hicken
  • Patent number: 8341344
    Abstract: A technique of accessing a resource includes receiving, at a master scheduler, resource access requests. The resource access requests are translated into respective slave state machine work orders that each include one or more respective commands. The respective commands are assigned, for execution, to command streams associated with respective slave state machines. The respective commands are then executed responsive to the respective slave state machines.
    Type: Grant
    Filed: September 21, 2007
    Date of Patent: December 25, 2012
    Inventors: Guhan Krishnan, John Kalamatianos
  • Patent number: 8341379
    Abstract: In one embodiment, a processor comprises a memory management unit (MMU) and an interface unit coupled to the MMU and to an interface unit of the processor. The MMU comprises a queue configured to store pending hardware-generated page table entry (PTE) updates. The interface unit is configured to receive a synchronization operation on the interface that is defined to cause the pending hardware-generated PTE updates, if any, to be written to memory. The MMU is configured to accept a subsequent hardware-generated PTE update generated subsequent to receiving the synchronization operation even if the synchronization operation has not completed on the interface. In some embodiments, the MMU may accept the subsequent PTE update responsive to transmitting the pending PTE updates from the queue. In other embodiments, the pending PTE updates may be identified in the queue and subsequent updates may be received.
    Type: Grant
    Filed: May 5, 2010
    Date of Patent: December 25, 2012
    Assignee: Apple Inc.
    Inventors: Jesse Pan, Ramesh Gunna
  • Patent number: 8341355
    Abstract: Mechanisms for accessing a set associative cache of a data processing system are provided. A set of cache lines, in the set associative cache, associated with an address of a request are identified. Based on a determined mode of operation for the set, the following may be performed: determining if a cache hit occurs in a preferred cache line without accessing other cache lines in the set of cache lines; retrieving data from the preferred cache line without accessing the other cache lines in the set of cache lines, if it is determined that there is a cache hit in the preferred cache line; and accessing each of the other cache lines in the set of cache lines to determine if there is a cache hit in any of these other cache lines only in response to there being a cache miss in the preferred cache line(s).
    Type: Grant
    Filed: May 25, 2010
    Date of Patent: December 25, 2012
    Assignee: International Business Machines Corporation
    Inventors: Jian Li, William E. Speight, Lixin Zhang
  • Patent number: 8335902
    Abstract: Backup systems and methods are disclosed for a virtual computing environment. Certain examples include a system having a backup management server that communicates with a host server having at least one virtual machine. The management server coordinates with the host server to perform backup copies of entire virtual machine disks from outside the guest operating system of the virtual machine. In certain examples, such backup systems further utilize a volume shadow copy service executing on the host server to quiesce virtual machine applications to put data in a consistent state to be backed up. The backup system then utilizes hypervisor snapshot capabilities of the host server to record intended changes to the virtual machine disk files while such files are being copied (e.g., backed up) by the host server. Such recorded changes can be later committed to the virtual machine disk files once the backup operation has completed.
    Type: Grant
    Filed: April 16, 2012
    Date of Patent: December 18, 2012
    Assignee: Vizioncore, Inc.
    Inventor: David Allen Feathergill
  • Patent number: 8335886
    Abstract: A method of executing a wear leveling operation within a non-volatile memory including a single-level memory cell block (SLC) and a multi-level memory cell block (MLC) is disclosed. The method includes calculating an average erase point in relation to a number of programming/erase (P/E) operations applied to a logical block address (LBA), a SLC mode usage point in relation to a number of the P/E operations applied to the SLC, a MLC mode usage point in relation to a number of the P/E operations applied to the MLC, and a wear value in relation to the average erase point, the SLC mode usage point, and the MLC mode usage point; and then if the wear value exceeds a defined threshold value, performing the wear leveling operation.
    Type: Grant
    Filed: August 3, 2009
    Date of Patent: December 18, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Yang-sup Lee
  • Patent number: 8332589
    Abstract: Method, system, and computer program product embodiments for, in a computing storage environment for destaging data from nonvolatile storage (NVS) to a storage unit, identifying working data on a stride basis by a processor device are provided. A multi-update bit is established for each stride in a modified cache. The multi-update bit is adapted to indicate at least one track in a working set. A schedule of destage scans is configured based on a plurality of levels of urgency. A destage operation is performed based on at least one of a number of strides examined by the destage scans, whether the multi-update bit is set, and whether an emergency level of the plurality of levels of urgency is active.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: December 11, 2012
    Assignee: International Business Machines Corporation
    Inventors: Brent C. Beardsley, Michael T. Benhase, Lokesh M. Gupta, Joseph S. Hyde, II, Sonny E. Williams
  • Patent number: 8332596
    Abstract: An error message handling buffer comprises a first buffer and a second buffer. A first index is associated with the first buffer and a second index is associated with the second buffer. A buffer controller is operable to write and read messages in the buffer, such that messages are written to the buffer of the first and second buffers that has a buffer index value lesser than the buffer size, and read from the other of the first and second buffers, the other buffer having an index value greater than or equal to the buffer size.
    Type: Grant
    Filed: June 12, 2009
    Date of Patent: December 11, 2012
    Assignee: Cray Inc.
    Inventor: Clayton D. Andreasen
  • Patent number: 8327094
    Abstract: The present invention transfers replication logical volumes between and among storage control units in a storage system comprising a plurality of storage control units. To transfer replication logical volumes from a storage control unit to a storage control unit, a virtualization device sets a path to the storage control unit. The storage control unit then prepares a differential bitmap in order to receive access requests. When the preparation is completed, the virtualization device makes access requests to the storage control unit. The storage control unit then hands over the access requests to the storage control unit. Subsequently, the storage control unit performs a process so that the access requests are reflected in a disk device and performs an emergency destage of storing data in a cache memory into disk device. When the emergency destage is ended, the storage control unit connects to an external storage control unit and hands over access requests to the external storage control unit.
    Type: Grant
    Filed: March 18, 2010
    Date of Patent: December 4, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Ai Satoyama, Yoshiaki Eguchi, Yasutomo Yamamoto
  • Patent number: 8327058
    Abstract: Described herein are system(s) and method(s) for routing data in a parallel Turbo decoder. Aspects of the present invention address the need for reducing the physical circuit area, power consumption, and/or latency of parallel Turbo decoders. According to certain aspects of the present invention, address routing-networks may be eliminated, thereby reducing circuit area and power consumption. According to other aspects of the present invention, address generation may be moved from the processors to dedicated address generation modules, thereby decreasing connectivity overhead and latency.
    Type: Grant
    Filed: July 25, 2008
    Date of Patent: December 4, 2012
    Assignee: Broadcom Corporation
    Inventors: Tak (Tony) Lee, Bazhong Shen
  • Patent number: 8327108
    Abstract: An electronic slave device includes a hardware data packing block having a configurable multiplexing unit having inputs connected to system bus, wires for receiving in parallel each bit of a data word, outputs connected to the respective data write pins of a memory for outputting in parallel each bit of a rearranged data word to be recorded, and rearrangeable connections between the inputs and the outputs according to a set configuration; a format register, the value of which can be set by an external master device to at least two different values; and a logic circuit capable of setting the connections of the multiplexing unit according to the value of the format register to obtain a rearranged data word having at least one symbol with a shifted position in comparison with the position of this symbol in the received data word.
    Type: Grant
    Filed: October 20, 2006
    Date of Patent: December 4, 2012
    Assignee: ST-Ericsson SA
    Inventors: Daineche Layachi, Emmanuel Alie, Laurent Capella
  • Patent number: 8321636
    Abstract: Memory reallocation and sharing among components of an electronic system is provided. The electronic system includes a first memory area coupled for access by a first processor via a first bus, and a second memory area coupled for access by a second processor via a second bus. An example system includes a central processor as the first processor and a digital signal processor as the second processor. The electronic system further includes memory configurations that support shared access of the second memory area by the first processor. Using shared access, the first processor can directly access the second memory via the first bus or indirectly access the second memory via the second bus and the second processor. The memory sharing also includes partitioning the shared memory to simultaneously provide the first processor with direct and indirect access to the shared memory.
    Type: Grant
    Filed: March 6, 2006
    Date of Patent: November 27, 2012
    Assignee: CSR Technology Inc.
    Inventors: Nicolas P. Vantalon, Steven A. Gronemeyer, Vojislav Protic
  • Patent number: 8316199
    Abstract: In a system which realizes to prevent leakage/loss of secret information by prohibiting a write operation to a secondary storage apparatus and a write operation to an external medium, an automatic collection of secret data to a server is executed, an existing application mode of PC is not damaged, and then an update of OS and an application is executed. The present invention places a secondary storage apparatus write control driver on the lower level than a file system, and redirects a write operation to the secondary storage apparatus, setting up a memory to be a primary cache, and cache data file on a cache server of a network destination to be a secondary cache. Thereby, the write operation to the secondary storage apparatus is not executed, and difference data is stored on the cache server, so that the automatic collection of secret data to the server can be realized.
    Type: Grant
    Filed: November 7, 2006
    Date of Patent: November 20, 2012
    Assignee: Hitachi Solutions, Ltd.
    Inventor: Yasuhiro Kirihata
  • Patent number: 8316187
    Abstract: Disclosed is a cache memory, design structure, and corresponding method for improving cache performance comprising one or more cache lines of equal size, each cache line adapted to store a cache block of data from a main memory in response to an access request from a processor; and a predict buffer, of size equal to the size of the cache lines, configured to store a next block of data from said main memory in response to a predict-fetch signal generated using at least one previous access request.
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: November 20, 2012
    Assignee: International Business Machines Corporation
    Inventor: Anil Pothireddy
  • Patent number: 8316213
    Abstract: Systems and methods for managing mapping information for objects maintained in a distributed storage system are provided. The distributed storage system can include a keymap subsystem that manages the mapping information according to object keys. Requests for specific object mapping information are directed to specific keymap coordinators within the keymap subsystem based on a consistency based hashing schema. The hashing schema is updated and distributed to other components within the distributed storage system based on a defined distribution model.
    Type: Grant
    Filed: July 31, 2009
    Date of Patent: November 20, 2012
    Assignee: Amazon Technologies, Inc.
    Inventors: James Christopher Sorenson, III, Gunavardhan Kakulapati, Jason G. McHugh, Allan H. Vermeulen
  • Patent number: 8316178
    Abstract: Described embodiments provide a method of transferring, by a media controller, data associated with a host data transfer between a host device and a storage media. A buffer layer module of the media controller segments the host data transfer into one or more data transfer segments. Each data transfer segment corresponds to at least a portion of the data. The buffer layer module allocates a number of physical buffers to a virtual circular buffer for buffering the one or more data transfer segments. The buffer layer module transfers, by the virtual circular buffer, each of the data transfer segments between the host device and the storage media through the allocated physical buffers.
    Type: Grant
    Filed: March 25, 2010
    Date of Patent: November 20, 2012
    Assignee: LSI Corporation
    Inventors: Timothy Lund, Carl Forhan, Michael Hicken
  • Patent number: 8316204
    Abstract: One embodiment of the present invention provides a system that uses versioned pointers to facilitate reusing memory without having to reclaim the objects solely through garbage collection. The system operates by first receiving a request to allocate an object. Next, the system obtains the object from a pool of free objects, and sets an allocated/free flag in the object to indicate that the object is allocated. The system also increments a version number in the object, and also encodes the version number into a pointer for the object. The system then returns the pointer, which includes the encoded version number. In this way, subsequent accesses to the object through the pointer can compare the version number encoded in the pointer with the version number in the object to determine whether the object has been reused since the pointer was generated.
    Type: Grant
    Filed: September 28, 2011
    Date of Patent: November 20, 2012
    Assignee: Oracle America, Inc.
    Inventor: David R. Chase
  • Patent number: 8316205
    Abstract: A storage system having a primary storage apparatus for storing data from a host computer in a primary logical volume, and a secondary storage apparatus connected to the primary storage apparatus, for providing a secondary logical volume for storing a copy of the data, the storage system comprising: a search unit for checking whether or not data exists in each primary slot area formed by partitioning a storage area in the primary logical volume into predetermined storage areas; a transmission unit for sending, if no data is held in the primary slot area, a notice indicating no data stored to the secondary storage apparatus; and a data write unit for writing, when the notice is received from the primary storage apparatus, zero data in the secondary slot area.
    Type: Grant
    Filed: November 15, 2011
    Date of Patent: November 20, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Makoto Deguchi, Hidenori Suzuki
  • Patent number: 8316203
    Abstract: A storage system for storage of data written from a computer, and when a write request of data to a first logical volume is received, the data on request is stored into the first logical volume. When a first-generation snapshot creation request is received, the data stored in the first logical volume at the time of receiving the first-generation snapshot creation request is written into a pool region as data corresponding to a first-generation snapshot, and when a second-generation snapshot creation request is received, any portion of the data updated after the first-generation snapshot creation request is received but before the second-generation snapshot creation request is issued is read from the first logical volume for writing into the pool region. Such a storage system favorably implements snapshot backup with no dependency with a positive volume in terms of performance and failure, and with high capacity efficiency.
    Type: Grant
    Filed: January 13, 2009
    Date of Patent: November 20, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Yoshiaki Eguchi, Shunji Kawamura