Patents Examined by Yair Leibovich
  • Patent number: 11586364
    Abstract: A memory management method is provided according to the invention. The method includes: reading a physical unit and updating a read count of the physical unit; scanning the physical unit if the updated read count is not less than a read count threshold; and adjusting the read count threshold according to the read count and a read error bit. Therefore, a data unit that needs to be scanned can be determined to reduce unnecessary data scanning.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: February 21, 2023
    Assignee: Hefei Core Storage Electronic Limited
    Inventors: Xin Hu, Liang Xu, Xiaoyang Zhang, Zhi Wang
  • Patent number: 11586498
    Abstract: Devices and techniques to recover data from a memory device using a custom Read Retry feature are disclosed herein. A memory device can receive a first read request, read data from the memory array corresponding to the read request, and determine if the read data corresponding to the first read request includes a detectable error. In response to a detected error in the received data corresponding to the first read request, the memory device can recover data corresponding to the first read request using one of a set of read retry features, and load the one of the set of read retry features used to recover data corresponding to the first read request as a custom read retry feature in the memory device for a second read request subsequent to the first read request.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: February 21, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Rahul Mitchell Jairaj, Mark A. Hawes, Terry M. Grunzke
  • Patent number: 11561870
    Abstract: An improved solid state drive (SSD). The SSD comprising a plurality of non-volatile memory dies, each configured to store at least one block of data associated with one of a plurality of superblocks each containing a plurality of blocks; a volatile memory; and a memory controller. The memory controller configured to store a bit map associated with a first superblock of the plurality of superblocks in the volatile memory, wherein the bit map is configured to indicate whether each of the plurality of blocks is a replacement block, store a block address list in the volatile memory, the block address list is configured to store an address of one or more replacement blocks, and store a replacement block index in the volatile memory associated with the first superblock of the plurality of superblocks, the replacement block index corresponding to the location of an address of a first replacement block of the first superblock in the block address list.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: January 24, 2023
    Assignee: Kioxia Corporation
    Inventor: Amit Jain
  • Patent number: 11550647
    Abstract: Systems and methods for adaptive fault prediction analysis are described. In one embodiment, the system includes one or more computing components, and one or more hardware controllers. In some embodiments, the storage system includes a storage drive. At least one of the one or more hardware controllers is configured to analyze one or more tolerance limits of a first computing component among the plurality of computing components; calculate a failure metric of the first computing component based at least in part on the analysis of the one or more tolerance limits of the first computing component; analyze sensor data from the first computing component in real time; and update the failure metric based at least in part on the analyzing of the sensor data.
    Type: Grant
    Filed: March 2, 2021
    Date of Patent: January 10, 2023
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventors: Deepak Nayak, Hemant Mohan
  • Patent number: 11544002
    Abstract: A memory system, a memory controller and an operating method are disclosed. When a target command which instructs an operation of writing target data to a memory device is received from a host, the target data is divided into data units, and a first data unit among the data units is controlled such that the entire first data unit is written to the memory device or none of the first data unit is written to the memory device. As a consequence, it is possible to write data in specific units in a memory system using a multi-core.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: January 3, 2023
    Assignee: SK hynix Inc.
    Inventors: Dae Hoon Jang, Dong Ham Yim, Young Hoon Cha, Young Guen Choi, Jeong Sun Park, Cheon Ok Jeong
  • Patent number: 11544132
    Abstract: A CCI (I3C SDR) processing section determines status of an index when requested to be accessed by an I3C master for a read operation. An error handling section then controls an I3C slave 13 to detect occurrence of an error based on the status of the index and to neglect all communication until communication is restarted or stopped by the I3C master, the I3C slave 13 being further controlled to send a NACK response when performing acknowledge processing on a signal sent from the I3C master. This technology can be applied to the I3C bus, for example.
    Type: Grant
    Filed: July 20, 2018
    Date of Patent: January 3, 2023
    Assignee: Sony Semiconductor Solutions Corporation
    Inventors: Hiroo Takahashi, Naohiro Koshisaka
  • Patent number: 11537481
    Abstract: The exemplary embodiments are related to a device, a system, and a method for implementing a hardware mechanism that is configured to validate the performance of scheduling software utilized by a safety-critical system. The hardware device may receive an indication that a first frame of a frame schedule is in use. The hardware device may also monitor a time parameter corresponding to the first frame. The hardware device may also determine whether an indication that a second frame of the frame schedule is in use is received prior to the expiration of the time parameter. When the indication that the second frame of the frame scheduler is in use is not received prior to the expiration of time parameter, the hardware device may send a signal to an operating system of the safety-critical system indicating that an error in executing the frame scheduled has occurred.
    Type: Grant
    Filed: January 9, 2020
    Date of Patent: December 27, 2022
    Assignee: WIND RIVER SYSTEMS, INC.
    Inventors: Mark Dapoz, Martin Cocking
  • Patent number: 11532372
    Abstract: Memory systems and method of operating the same enable debugging of a memory system with vendor unique (VU) commands without using a physical cable connection to a debugging port on the memory system. In one aspect, a Universal Asynchronous Receiver-Transmitter (UART) protocol is serialized over a VU host protocol. In another aspect, Joint Test Action Group (JTAG) may be performed over UART or serial advanced technology attachment (SATA).
    Type: Grant
    Filed: July 5, 2019
    Date of Patent: December 20, 2022
    Assignee: SK hynix Inc.
    Inventors: Andrei Konan, Sergei Peniaz
  • Patent number: 11533220
    Abstract: The concepts and technologies disclosed herein are directed to a network-assisted Raft consensus protocol, referred to herein as “NetRaft.” According to one aspect of the concepts and technologies disclosed herein, a system can include a plurality of servers operating in a server cluster, and a plurality of P4 switches corresponding to the plurality of servers. Each server of the plurality of servers can include a back-end that executes a complete Raft algorithm to perform leader election, log replication, and log commitment of a Raft consensus algorithm. Each P4 switch of the plurality of P4 switches can include a front-end that executes a partial Raft algorithm to perform the log replication and the log commitment of the Raft consensus algorithm. The back-end can maintain a complete state for responding to requests that cannot be fulfilled by the front-end. The requests can include read requests and/or write requests.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: December 20, 2022
    Assignees: AT&T Intellectual Property I, L.P., Regents of the University of Minnesota
    Inventors: Bo Han, Vijay Gopalakrishnan, Marco Platania, Zhi-Li Zhang, Yang Zhang
  • Patent number: 11531601
    Abstract: A memory controller includes a command queue, a memory interface queue, at least one storage queue, and a replay control circuit. The command queue has a first input for receiving memory access commands. The memory interface queue receives commands selected from the command queue and couples to a heterogeneous memory channel which is coupled to at least one non-volatile storage class memory (SCM) module. The at least one storage queue stores memory access commands that are placed in the memory interface queue. The replay control circuit detects that an error has occurred requiring a recovery sequence, and in response to the error, initiates the recovery sequence. In the recovery sequence, the replay control circuit transmits selected memory access commands from the at least one storage queue by grouping non-volatile read commands together separately from all pending volatile reads, volatile writes, and non-volatile writes.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: December 20, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jing Wang, James R. Magro, Kedarnath Balakrishnan
  • Patent number: 11526414
    Abstract: In one aspect, a first device may download at least one disk image and then provide the disk image to second and third devices through a fourth device that controls connections to the second and third devices. The first device may then run computer diagnostics concurrently on the second and third devices through the fourth device and using the image provided to each of the second and third devices. In some examples, communication between the devices may occur using USB ports.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: December 13, 2022
    Assignee: Lenovo (Singapore) Pte. Ltd.
    Inventors: Marcelo da Costa Ferreira, Carlos Eduardo Dias Duarte, Gustavo Labbate Godoy
  • Patent number: 11526411
    Abstract: An information handling system includes a non-volatile storage device communicatively coupled to a boot processor and an application processor. The boot processor, prior to the execution of a hang sensitive transaction, stores information associated with the hang sensitive transaction at a memory device. The application processor is configured to detect a catastrophic failure of the hang sensitive transaction. In response to the detection of the catastrophic failure, the application processor retrieves the information stored at the memory device and store the information at the non-volatile storage device.
    Type: Grant
    Filed: February 13, 2020
    Date of Patent: December 13, 2022
    Assignee: Dell Products L.P.
    Inventors: Craig L. Chaiken, Siva Subramaniam Rajan
  • Patent number: 11520522
    Abstract: A method, computer program product, and computer system for identifying, by a computing device, information associated with a relationship between a physical layer block and a virtual logic block for RAID storage. The information associated with the relationship between the physical layer block and the virtual logic block may be written within the RAID storage. The physical layer block within the RAID storage may be rebuilt only when the physical layer block includes the information associated with the relationship between the physical layer block and the virtual logic block.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: December 6, 2022
    Assignee: EMC IP Holding Company, LLC
    Inventors: Nickolay Dalmatov, Mikhail Danilov
  • Patent number: 11520702
    Abstract: The present invention discloses a method and a system for managing cache memory. The system comprising a processor is configured to receive datasets from one or more applications, segregate the received datasets into one or more data blocks, identify a checkpoint from previously created checkpoints stored in a virtual cache corresponding to the one or more data blocks, wherein the checkpoints are previously created based on frequency of repetition of each of the one or more data blocks and association between the each of the one or more data blocks, recall a sequence of previously stored data blocks from main memory based on the identified checkpoint, and send the sequence of previously stored data blocks to the one or more applications for execution, thereby managing cache memory.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: December 6, 2022
    Assignee: Wipro Limited
    Inventors: Rishav Das, Sourav Mudi
  • Patent number: 11513915
    Abstract: A backup management system for providing data integrity services to an application host that hosts an application that uses application data includes storage for storing threshold values for creating an application backup and a processor programmed to monitor: a rate of change associated with the application data, and an input-output rate of the application data; make a determination, based on the threshold values, the rate of change, and the input-output rate, that an unscheduled backup for the application is to be generated; obtain a micro-backup for the application in response to the determination; and obtain a restoration ready backup for the application using the micro-backup and at least one previously generated backup.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: November 29, 2022
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Pradeep Viveki, Mahantesh Murageppa Ambaljeri, Mahesh Reddy Appireddygari Venkataramana
  • Patent number: 11500710
    Abstract: An application framework that provides field configuration of exception handlers by one or more applications, rather than defining exceptions at runtime. The exception handler may operate as a remote service in communication with an application executing locally. When an exception is received, the exception handler can consume the exception and return a defined object based on the exception type.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: November 15, 2022
    Assignee: T-MOBILE USA, INC.
    Inventor: Ravi Lagadapati
  • Patent number: 11487607
    Abstract: Automated recovery of execution roles in a distributed historian system in accordance with actions and rules customized to each execution role. A monitoring service monitors the health status of execution roles and automatically performs a corrective action in response to the health state of an execution role triggering a predetermined rule.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: November 1, 2022
    Assignee: AVEVA SOFTWARE, LLC
    Inventors: Brian Kenneth Erickson, Arun Kumar Nattamai Ramdoss, Vinay T. Kamath, Abhijit Manushree
  • Patent number: 11467923
    Abstract: In a first virtual storage device managed by a helper virtual machine, first data of a first application is stored, the first application executing on a first system, the helper virtual machine executing on a recovery system. Responsive to determining that a duplicate of the first application should be activated on the recovery system, a compute instance is spawned in a hypervisor executing on the recovery system. In the compute instance, a duplicate of the first application is provisioned. The first data is reassociated from the helper virtual machine to the provisioned duplicate application. The duplicate application is activated, the activating causing the duplicate application to execute on the second system using the first data.
    Type: Grant
    Filed: May 15, 2019
    Date of Patent: October 11, 2022
    Assignee: Kyndryl, Inc.
    Inventor: Rajagopal Vaideeswaran
  • Patent number: 11449402
    Abstract: Techniques for storage management involve: in response to a first disk becoming offline and remaining offline until a first time point, selecting a second storage slice in a second disk as a backup storage slice for a first storage slice in the first disk, the first storage slice being one of slices forming a redundant array of independent disks (RAID), the slices being located in different disks. The techniques further involve: writing, between the first time point and a second time point, data to be written into the first storage slice in the RAID to the second storage slice, the second time point being later than the first time point. The techniques further involve: in response to the first disk remaining offline until the second time point, replacing the first storage slice in the RAID with the second storage slice. Such techniques may improve performance of a RAID-based storage system.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: September 20, 2022
    Assignee: EMC IP Holding Company LLC
    Inventors: Baote Zhuo, Jibing Dong, Jian Gao, Jianbin Kang
  • Patent number: 11449393
    Abstract: A computer system includes a client device, and a server configured to monitor a status of a virtual computing session for failure, with the virtual computing session being accessed by the client device. The server redirects the client device to a backup virtual computing session based on failure of the virtual computing session, and updates a state of the backup virtual computing session to match a previous state of the virtual computing session prior to failure.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: September 20, 2022
    Assignee: CITRIX SYSTEMS, INC.
    Inventors: Juan C. Rivera, Christopher W. Midgley