Abstract: A system and method for forming post passivation discrete components, is described. High quality discrete components are formed on a layer of passivation, or on a thick layer of polymer over a passivation layer.

Abstract: A chip package structure having a substrate therein for accommodating a die. Power regions supplying power to various control units within the die are grouped together into at least two sections. At least one ? filter is used to isolate different power regions on the substrate so that cross interference of noise signals are reduced and stability of the chip is improved. The ? filter is positioned close to one of the corners of the substrate so that the layout of wiring on the substrate is facilitated.

Abstract: There are provided a method for evaluating, in a reduced number of steps, a property of an integrated circuit reflecting operating conditions for an actual LSI and the design of the LSI. The property (delay) of a circuit A (ring oscillator) in a wafer or mounted chip is measured actually or simulated and the property of a circuit B (LSI) is simulated. Then, the interrelation between the degree of property degradation of the circuit A and the degree of property degradation of the circuit B is determined. The circuit property of a circuit AA (ring oscillator) having substantially the same degree of property degradation as the circuit A and manufactured under a new manufacturing condition is measured actually or simulated so that the degree of property degradation of a circuit BB is predicted from the interrelation and the degree of property degradation of the circuit AA.

Abstract: A GaInP epitaxial stacking structure and fabrication method thereof, and a FET transistor using this structure are provided wherein, stacked upon a GaAs single-crystal substrate are at least a buffer layer, a GaZIn1-ZAs (0<Z?1) channel layer, and a GaYIn1?YP (0<Y?1) electron-supply layer joined to the channel layer, wherein the GaInP epitaxial stacking structure includes a region within the electron-supply layer wherein the gallium composition ratio (Y) decreases from the side of the junction interface with the channel layer toward the opposite side.

Abstract: The invention is directed to a liquid crystal display having two opposed substrates, a liquid crystalline medium contained between the substrates, and a plurality of electrodes arranged on the substrates to produce a multiplicity of pixels. According to the invention, the electrodes are configured in such fashion that the pixels have round contours. The pixels may also have contours in the form of a polygon with more than four sides. Preferably pixels with roughly circular contours are produced.

Abstract: The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon.

Abstract: Multi-color light-emissive displays in which the constituent light-emissive devices providing the multiple colors are laterally integrated on the surface of a substrate. The light-emissive devices, typically emitting light by electroluminescence, are arranged such that adjacent devices emit light of a differing wavelength or color. The semiconductor phosphor material forming the active element of each light-emissive device is laterally defined by a lift-off technique in which a patterned layer of a sacrificial material is formed on the substrate, a layer of the semiconductor phosphor material is deposited, and the sacrificial layer is removed to leave semiconductor phosphor material on the substrate in selected locations defined by the pattern. The lift-off technique is iterated to successively fabricate active elements for light-emissive devices of each differing wavelength constituting the multi-color display.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base. The heterojunction bipolar transistor further comprises a first nitride spacer and a second nitride spacer situated on the base, where the first nitride spacer and the second nitride spacer are separated by a distance substantially equal to a critical dimension. For example, the first nitride spacer and the second nitride spacer may comprise LPCVD or RTCVD silicon nitride. According to this exemplary embodiment, the heterojunction bipolar transistor further comprises an emitter situated between said first nitride spacer and said second nitride spacer, where the emitter has a width substantially equal to the critical dimension. The emitter may, for example, comprise polycrystalline silicon. In another embodiment, a method that achieves the above-described heterojunction bipolar transistor is disclosed.

Abstract: Disclosed is a method of fabricating gate dielectric for use in semiconductor device having a high dielectric constant comprising formation of a metal oxide or a metal silicate on a silicon substrate, nitridation to incorporate nitrogen component to said metal oxide and reoxidation of said metal oxide that contains said nitrogen component. In this invention, the nitridation can be performed via heat-treatment of the resulting product, wherein said metal oxide is formed within, in a nitrogen-containing gas atmosphere; performed by plasma treatment by exposing said metal oxide to a nitrogen-containing plasma atmosphere; or performed by ion instillation of nitrogen component to said metal oxide, thereby providing a gate dielectric for use in semiconductor device which is able to remarkably inhibit the increase in effective thickness resulted from a post heat-treatment at high temperature by forming a film of metal oxide such as ZrO2 followed by nitridation and reoxidation.

Abstract: The invention relates to a phase-change memory device that uses SOI in a chalcogenide volume of memory material. Parasitic capacitance, both vertical and lateral, are reduced or eliminated in the inventive structure.

Abstract: A method of forming a memory transistor includes providing a substrate comprising semiconductive material and forming spaced-apart source/drain structures. At least one of the source/drain structures forms a Schottky contact to the semiconductive material. The method also includes forming a memory gate between the spaced-apart source/drain structures and forming a control gate disposed operatively over the memory gate.

Abstract: An ESD device and method using parasitic bipolar transistors that are silicided. The first embodiment is a parasitic Bipolar Junction Transistor comprised of n+/n−/p−/n−/n+ regions. The emitter is formed of the second N+ region and the second N− well. The parasitic base is formed by the p− substrate or well. The collector is formed of the first well and the first n+ region. The benefit of the first embodiment is the trigger voltage is lower because the junction between the n− well (emitter) and P− substrate (base) and the junction between P− substrate (base) and the n-well have lower cross over concentrations. The second embodiment is similar to the first embodiment with the addition of the first gate. The first gate is preferably connected to the first n+ region and the Vpad. The third embodiment contains the same elements as the second embodiment with the addition of a third n+ region.

Abstract: A method of forming a buried wiring comprising the steps of: (A) forming a wiring and a first insulating layer filled between the wirings on a substratum, (B) immersing the first insulating layer in a fluid which can dissolve the first insulating layer, to dissolve the first insulating layer into the fluid, (C) substituting, for the fluid, a raw material solution containing a raw material for forming a second insulating layer, without bringing the wiring into contact with a gas, and (D) filling a second insulating layer formed by gelation in the raw material solution at least between the wirings, and then, drying off the raw material solution, thereby to form the second insulating layer at least between the wirings.

Abstract: The invention is a method of depositing an aluminum nitride comprising layer over a semiconductor substrate, a method of forming DRAM circuitry, DRAM circuitry, a method of forming a field emission device, and a field emission device. In one aspect, a method of depositing an aluminum nitride comprising layer over a semiconductor substrate includes positioning a semiconductor substrate within a chemical vapor deposition reactor. Ammonia and at least one of triethylaluminum and trimethylaluminum are fed to the reactor while the substrate is at a temperature of about 500° C. or less and at a reactor pressure from about 100 mTorr to about 725 Torr effective to deposit a layer comprising aluminum nitride over the substrate at such temperature and reactor pressure. In one aspect, such layer is utilized as a cell dielectric layer in DRAM circuitry. In one aspect, such layer is deposited over emitters of a field emission display.

Abstract: This invention relates to a memory cell which comprises a capacitor having a first electrode and a second electrode separated by a dielectric layer. Such dielectric layer comprises a layer of a semi-insulating material which is fully enveloped by an insulating material and in which an electric charge is permanently present or trapped therein. Such electric charge accumulated close to the first or to the second electrode, depending on the electric field between the electrodes, thereby defining different logic levels.

Abstract: In a copper plating process, a seed layer is uniformly deposited over a surface, including lining a high aspect ratio trench defined by that surface. A mask layer is provided using a process that fails to deposit in the trench. In one exemplary embodiment, the failure is due to the decrease in the isotropic flux of neutrals toward the bottom of the trench. Copper is subsequently electroplated. Because the seed layer is exposed only within the trench, copper deposits only therein. The self-aligned mask prevents plating outside of the trench. A chemical-mechanical planarization step removes the mask and the seed layer extending beyond the trench, leaving a copper structure within the trench. The structure may serve as a conductive line, an interconnect, or a capacitor plate.

Abstract: The invention includes a method of forming a capacitor electrode. A sacrificial material sidewall is provided to extend at least partially around an opening. A first silicon-containing material is formed within the opening to partially fill the opening, and is doped with conductivity-enhancing dopant. A second silicon-containing material is formed within the partially filled opening, and is provided to be less heavily doped with conductivity-enhancing dopant than is the first silicon-containing material. At least some of the second silicon-containing material is converted into hemispherical grain silicon, and at least some of the sacrificial material sidewall is removed. The invention also encompasses methods of forming capacitors and capacitor assemblies incorporating the above-described capacitor electrode. Further, the invention encompasses capacitor assemblies and capacitor structures.

Abstract: A honeycomb/webbed, high surface area capacitor formed by etching a storage poly using an etch mask having a plurality of micro vias. The etch mask is preferably formed by applying an HSG polysilicon layer on a surface of the storage poly with a mask layer being deposited over the HSG polysilicon layer. An upper portion of the mask layer is removed to expose the uppermost portions of the HSG polysilicon layer and the exposed HSG polysilicon layer portions are then etched, which translates the pattern of the exposed HSG polysilicon layer portions into the storage poly. The capacitor is completed by depositing a dielectric material layer over the storage poly layer and depositing a cell poly layer over the dielectric material layer.

Abstract: A semiconductor device having a chamfered silicide layer and a manufacturing method of the same. The semiconductor device includes: a first insulation layer overlying a semiconductor substrate; gate structures including first conductive layer patterns formed on the first insulation layer, and second conductive layer patterns which are formed on the first conductive layer patterns, wherein the lower sides of the second conductive layer patterns are substantially perpendicular to the major surface of the semiconductor substrate and the upper sides of the second conductive layer patterns are chamfered; and a second insulation layer formed with a first width W on the second conductive layer patterns, wherein the sidewalls of the second insulation layer overhang the upper edges of the second conductive layer patterns.

Abstract: Methods and apparatus are provided for forming a metal or metal silicide barrier layer. In one aspect, a method is provided for processing a substrate including positioning a substrate having a silicon material disposed thereon in a substrate processing system, depositing a first metal layer on the substrate surface in a first processing chamber, forming a metal silicide layer by reacting the silicon material and the first metal layer, and depositing a second metal layer in situ on the substrate in a second processing chamber. In another aspect, the method is performed in an apparatus including a load lock chamber, the intermediate substrate transfer region including a first substrate transfer chamber and a second substrate transfer chamber, a physical vapor deposition processing chamber coupled to the first substrate transfer chamber, and a chemical vapor deposition chamber coupled to the second substrate transfer chamber.