Abstract: A memory cell is defined along first, second, and third orthogonal dimensions and comprises an electrically conductive word line, an electrically conductive bit line, an electrical charge storage structure, a transistor structure, and a bit line contact. The charge storage structure is conductively coupled to the bit line via the transistor structure and the bit line contact. The transistor structure is conductively coupled to the word line. The first dimension is characterized by one-half of a bit line contact feature, one word line feature, one word line space feature, and one-half of a field poly line feature. The second dimension is characterized by two one-half field oxide features and one active area feature. The first and second dimensions define a 6F2 memory cell. The bit line contact feature is characterized by a contact hole bounded by insulating side walls.

Abstract: A method of forming a corrugated capacitor on a semiconductor component. The method of forming the corrugated capacitor comprises a series of depositing alternating layers of doped silicon glass having different etch rates on a semiconductor component, covering the alternating layers with an etch-resistant material, and etching the alternating layers, thereby forming a capacitor structure having corrugated sides.

Abstract: A method and system for manufacturing an MIM capacitor for utilization with a logic-based embedded DRAM device. At least one transistor, an interlayer dielectric, at least one contact and at least one metal one layer are generally formed on a substrate during a front end manufacturing operation of the capacitor on the substrate. An inter-metal dielectric layer is deposited upon the substrate, followed thereafter by a chemical mechanical polishing operation. Additionally, a lithographic operation is performed upon the substrate. Also, at least one dielectric deposition layer is generally on the substrate, followed thereafter by a chemical mechanical polishing operation and a stop on an oxide layer formed on the substrate. At least one metal two layer may then be formed on substrate and associated layers thereof, thereby resulting in the formation of a capacitor fully compatible with logic-based devices and processes thereof.

Abstract: In the fabrication of a MOS transistor, a single process step is performed for controlling the threshold voltage of the transistor and improving the reliability of a gate insulating film so that the number of manufacturing steps is decreased. A desired amount of fixed electric charge is provided at an interface between a semiconductor substrate and the gate insulating film by a nitriding process performed on the gate insulating film to form a channel region and control the threshold voltage of the MOS transistor, so that both an improvement in the reliability of the gate insulating film and control of the threshold voltage of the MOS transistor are performed in one step.

Abstract: A memory cell having a bit line contact is provided. The memory cell may be a 6F2 memory cell. The bit line contact may have a contact hole bounded by insulating sidewalls, and the contact hole may be partially or completely filled with a doped polysilicon plug. The doped polysilicon plug may have an upper plug surface profile that is substantially free of concavities or substantially convex. Similarly, a storage node contact may comprise a doped polysilicon plug having an upper plug surface profile that is substantially free of concavities or that is substantially convex. Additionally, a semiconductor device having a conductive contact comprising a polysilicon plug may is provided. The plug may contact a capacitor structure.

Abstract: Simplified method of manufacturing liquid crystal displays. A gate wire including a gate line, a gate pad and a gate electrode is formed on the substrate by using the first mask. A gate insulating layer, a semiconductor layer, a ohmic contact layer and a metal layer are sequentially deposited to make a quadruple layers, and patterned by a dry etch of using the second mask. At this time, the quadruple layers is patterned to have a matrix of net shape layout and covering the gate wire. An opening exposing the substrate is formed in the display area and a contact hole exposing the gate pad is formed in the peripheral area. Next, ITO is deposited and a photoresist layer coated on the ITO. Then, the ITO layer is patterned by using the third mask and a dry etch, and the data conductor layer and the ohmic contact layer not covered by the ITO layer is dry etched.

Abstract: It is an object of the present invention to provide a semiconductor device capable of decreasing electric resistance of a lower electrode provided therein, as well as capable of accurately responding to external signals having high frequencies inputted therein. The lower electrode 7 consists of three layers such as a silicon lower electrode layer 7a made of poly-crystalline silicon, a tungsten-silicide layer 7b made of tungsten silicide as a chemical compound of tungsten and silicon, and a protection layer 7c made of poly-crystalline silicon. By constructing the semiconductor device as described above, oxidation of the tungsten-silicide layer 7b may be prevented by the protection layer 7c made of poly-crystalline silicon even when oxidation layers of an ONO (silicon oxidation) layer 11 is formed by thermal oxidation. Consequently, electric resistance of the lower electrode 7 can be decreased.

Abstract: A semiconductor device comprises an SOI substrate, a trench, a trench capacitor, and a conductive layer. The SOI substrate includes a fist semiconductor region, a buried insulating film formed on the first semiconductor region, and a second semiconductor region formed on the buried insulating film. The trench is of a depth to reach the first semiconductor region, extending from a surface of the second semiconductor region on the SOI substrate and passing through the buried insulating film. The trench capacitor is formed within the trench. The conductive layer is formed in a region between a sidewall portion of the trench and the buried insulating film, and electrically connects the first semiconductor region and the second semiconductor region.

Abstract: A method of producing a SOI MOSFET which includes a fully depleted channel region of a first conductivity type formed in a top semiconductor layer disposed on an insulative substrate, source/drain regions of a second conductivity type formed to sandwich the channel region and a gate electrode formed on the channel region with intervention of a gate insulating film, the method comprises: forming the channel region by setting an impurity concentration of channel edge regions of the channel region adjacent to the source/drain regions higher than an impurity concentration of a channel central region of the channel region, and setting a threshold voltage Vth0 of the channel central region and a threshold voltage Vthedge of the channel edge regions so that a change of the threshold voltage Vth0 with respect to a change of the thickness of the top semiconductor layer and a change of the threshold voltage Vthedge with respect to the change of the thickness of the top semiconductor layer are of opposite sign.

Abstract: A method of manufacturing an interlayer dielectric film by vacuum ultraviolet CVD including the steps of placing a wafer in a vacuum chamber having a window; causing a first gas that contains silicon atoms to flow through the vacuum chamber; exposing the wafer to light emitted from a Xe2 excimer lamp through the window; and maintaining an atmosphere in the chamber at a first temperature which is less than 350° C. to form an insulating film on the wafer which substantially fills stepped portions of the wafer to provide step coverage and which has a substantially flat top surface.

Abstract: A semiconductor device includes: a semiconductor substrate having a memory cell section and a peripheral circuit section defined in a plane; a floating gate electrode formed on semiconductor substrate in the memory cell section; a control gate electrode laminated thereabove; a gate electrode as a peripheral circuit electrode formed in one-layer-structure on semiconductor substrate in the peripheral circuit section; a first dummy electrode formed in the peripheral circuit section so as to have approximately same thickness as floating gate electrode; and a second dummy electrode laminated thereabove so as to have approximately same thickness as control gate electrode.

Abstract: A method of forming an electrical isolation trench in a silicon-on-insulator (SOI) structure. The method comprises forming a first oxide layer on top of the upper silicon layer of the SOI structure, forming a polysilicon layer on top of said oxide layer, forming a second oxide layer on top of said polysilicon layer, patterning the first oxide layer, polysilicon layer, and second oxide layer to provide an etch mask, etching the upper silicon layer of the SOI structure to form said trench, and removing said second oxide layer and said polysilicon layer.

Abstract: A first source-drain region, a channel region, and a second source-drain region are arranged one after another in a semiconductor substrate. At least the surface of the channel region and parts of the first source-drain region are covered by a dielectric layer. A ferroelectric layer is disposed on the surface of the dielectric layer between two polarization electrodes. A gate electrode is arranged on the surface of the dielectric layer. The thickness of the dielectric layer is dimensioned such that a remanent polarization of the ferroelectric layer, which is aligned between the two polarization electrodes, produces compensation charges in part of the channel region. The ferroelectric transistor is suitable as a memory cell for a memory cell configuration.

Abstract: The HF defect density in an SOI is reduced. After annealing step (S2) of annealing an SOI at a temperature between the melting point (e.g., 993° C.) of a semiconductor metal compound (e.g., nickel silicide) formed from a metal and the semiconductor material of the crystal semiconductor of the SOI (inclusive) and the melting point of the semiconductor material (inclusive), the temperature is reduced such that the cooling rate within the temperature range from the melting point of the semiconductor metal compound and the production temperature (e.g., 775° C.) of the semiconductor metal compound becomes 0.12° C./sec or more.

Abstract: The present invention provides a double gated transistor and a method for forming the same that results in improved device performance and density. The preferred embodiment of the present invention provides a double gated transistor with asymmetric gate doping, where one of the double gates is doped degenerately n-type and the other degenerately p-type. By doping one of the gates n-type, and the other p-type, the threshold voltage of the resulting device is improved. Additionally, the preferred transistor design uses an asymmetric structure that results in reduced gate-to-drain and gate-to-source capacitance. In particular, dimensions of the weak gate, the gate that has a workfunction less attractive to the channel carriers, are reduced such that the weak gate does not overlap the source/drain regions of the transistor. In contrast the strong gate, the gate having a workfunction that causes the inversion layer to form adjacent to it, is formed to slightly overlap the source/drain regions.

Abstract: A semiconductor device with a package size close to its chip size is, apart from a stress absorbing layer, such as to effectively absorb thermal stresses. A semiconductor device (150) has a semiconductor chip provided with electrodes (158), a resin layer (152) forming a stress relieving layer provided on the semiconductor chip, wiring (154) formed from the electrodes (158) to over the resin layer (152), and solder balls (157) formed on the wiring (154) over the resin layer (152); the resin layer (152) is formed so as to have a depression (152a) in the surface, and the wiring (154) is formed so as to pass over the depression (152a).

Abstract: A high-breakdown voltage transistor (30; 30′) is disclosed. The transistor (30; 30′) is formed into a well arrangement in which a shallow, heavily doped, well (44) is disposed at least partially within a deeper, more lightly-doped well (50), both formed into an epitaxial layer (43) of the substrate (42). The deep well (50) is also used, by itself, for the formation of high-voltage transistors, while the shallower well (44) is used by itself in low-voltage, high-performance transistors. This construction permits the use of high-performance, and precisely matching, transistors in high bias voltage applications, without fear of body-to-substrate (or “back-gate-to-substrate”) junction breakdown.

Abstract: In the first aspect of the invention, a semiconductor device can effectively suppress the adverse short channel effect and the possible occurrence of junction leak current and has a low resistance diffusion layer to realize a short propagation delay time as a plurality of side wall films 4, 5 are formed at least in a part of the area between the gate electrode 3 and an elevated region 8 by laying a plurality of films in an appropriate order.

Abstract: A method of forming a metal wiring in a semiconductor device. A copper wiring is formed by means of CECVD method by which a chemical enhancer layer is utilized for increasing the deposition speed of copper. The damascene pattern is filled by means of MOCVD method using a copper precursor in order to increase the deposition speed. The chemical enhancer layer rises to the surface of copper after deposition of copper by a CECVD method and then the relatively high resistivity chemical enhancer layer that has risen to the surface of copper by plasma process is removed. Therefore, the ultra-fine damascene pattern can be rapidly filled with copper without increasing the resistance of the copper wiring.

Abstract: A semiconductor device is presented which is directed to a method of forming embedded DRAM and logic devices, where the DRAM devices are formed in bulk, single crystalline semiconductor regions and logic devices are formed in silicon-on-insulator (“SOI”) regions and where buried, doped glass is used as a mask to form deep trenches for storage in the bulk region. The resulting structure is also disclosed.