Abstract: A highly reliable semiconductor device which includes an oxide semiconductor is provided. Alternatively, a transistor having normally-off characteristics which includes an oxide semiconductor is provided. The transistor includes a first conductor, a first insulator, a second insulator, a third insulator, a first oxide, an oxide semiconductor, a second conductor, a second oxide, a fourth insulator, a third conductor, a fourth conductor, a fifth insulator, and a sixth insulator. The second conductor is separated from the sixth insulator by the second oxide. The third conductor and the fourth conductor are separated from the sixth insulator by the fifth insulator. The second oxide has a function of suppressing permeation of oxygen as long as oxygen contained in the sixth insulator is sufficiently supplied to the oxide semiconductor through the second oxide. The fifth insulator has a barrier property against oxygen.

Abstract: Dark current of FD is eliminated in an image sensor, and conversion efficiency of converting electric charge to voltage is improved. A pixel circuit includes a photoelectric conversion portion, a control transistor, and an electric charge accumulation portion. The photoelectric conversion portion converts light incident along an optical axis to electric charge. The control transistor controls output voltage according to input voltage. The electric charge accumulation portion accumulates electric charge in a region positioned between the control transistor and the photoelectric conversion portion on the optical axis, and supplies a voltage according to the amount of accumulated electric charge as the input voltage to the control transistor.

Abstract: The present disclosure provides a test element unit, an array substrate, a display panel, a display apparatus and a corresponding manufacturing method. The test element unit includes: a plurality of layers of test patterns, each layer of test pattern including at least one test block and at least one capacitor being formed between test blocks located in different layers, and, two electrodes of each of capacitors being two test blocks located in different layers, respectively, so that it can determined whether or not corresponding components and devices formed in the display region meet requirements by detecting the test patterns formed in the test region.

Abstract: A stacked-thin-film structure that includes an Llo-ordered MnAl layer having high perpendicular magnetic anisotropy (PMA). In some embodiments, the Ll0-ordered MnAl layer has an Mn content in a range of about 35% to about 65%, a thickness less than about 50 nm, a saturation magnetization of about 100 emu/cm3 to about 600 emu/cm3 and a magnetocrystalline anisotropy of at least 1×106 erg/cm. In some embodiments, the high-PMA Llo-ordered MnAl material is incorporated in magnetic tunneling junction stacked-film structures that are part of magnetoelectronic circuitry, such as spin-transfer-torque magnetoresistive random access memory circuitry and magnetic logic circuitry. In some embodiments, the high-PMA Llo-ordered MnAl material is incorporated into other devices, such as into read/write heads and/or recording media of hard-disk-drive devices.

Abstract: A display device includes a back board, a substrate, a display layer, and a cover lens. The back board includes a first portion, a second portion, and a bendable portion. The bendable portion is between the first portion and the second portion and separating the first portion from the second portion, and a rigidity of the bendable portion is smaller than a rigidity of the first portion and the second portion. The substrate is disposed on the first portion, the second portion, and the bendable portion, and the substrate is attached to the back board by an adhesive. The display layer is disposed on the substrate. The cover lens is disposed on the display layer.

Abstract: A micro-transfer printed intermediate structure comprises an intermediate substrate and one or more pixel structures disposed on the intermediate substrate. Each pixel structure includes an LED, a color filter, and a fractured pixel tether physically attached to the pixel structure. A fractured intermediate tether is physically attached to the intermediate substrate. A method of making an intermediate structure source wafer comprises providing a source wafer having a patterned sacrificial layer including sacrificial portions separated by anchors, disposing an intermediate substrate over the patterned sacrificial layer, and disposing one or more pixel structures on the intermediate substrate entirely on or over each sacrificial portion. Each pixel structure includes an LED, a color filter, and a fractured pixel tether physically attached to the pixel structure to form an intermediate structure.

Abstract: A semiconductor component, which includes a substrate, an interfacial layer disposed on the substrate, a first metal gate structure and a second metal gate structure disposed on the substrate. The first metal gate structure includes a first high-k dielectric layer disposed on the interfacial layer, and a first metal gate layer disposed on the first high-k dielectric layer. The second metal gate structure includes a second high-k dielectric layer disposed on the interfacial layer, a third high-k dielectric layer disposed on the second high-k dielectric layer, and a second metal gate layer disposed on the third high-k dielectric layer.

Abstract: Embodiments of the present disclosure are directed towards techniques and configurations for hybrid carbon-metal interconnect structures in integrated circuit assemblies. In one embodiment, an apparatus includes a substrate, a metal interconnect layer disposed on the substrate and configured to serve as a growth initiation layer for a graphene layer and the graphene layer, wherein the graphene layer is formed directly on the metal interconnect layer, the metal interconnect layer and the graphene layer being configured to route electrical signals. Other embodiments may be described and/or claimed.

Abstract: An optical waveguide for optical signals is formed in a semiconductor layer of an SOI substrate, a heater for heating the optical waveguide is formed on a silicon oxide film which covers the optical waveguide, and wirings for supplying power to the heater are connected to both ends of the heater. Each of the wirings is constituted of a laminated film of a bottom barrier metal film, an aluminum-copper alloy film serving as a main conductive film and a top barrier metal film, and the heater is constituted integrally with the bottom barrier metal film constituting a part of each of the wirings.

Abstract: A light emitting component is disclosed. In an embodiment a light-emitting device includes at least one active layer stack configured to generate light, a first electrode electrically contacting the at least one active layer stack, a second electrode electrically contacting the at least one active layer stack and at least one light-emitting face for emitting light. The device further includes a first contact structure electrically conductively connected to the first electrode and a second contact structure electrically conductively connected to the second electrode, wherein the first contact structure laterally surrounds a major part of the at least one light-emitting face and a major part of the second contact structure, and wherein the second contact structure laterally surrounds a major part of the at least one light-emitting face.

Abstract: A package substrate including a carrier, a first patterned conductive layer, a second patterned conductive layer and a 3D-printing conductive wire is provided. The carrier has a first surface, a second surface and a third surface. The first surface is opposite to the second surface, and the third surface is connected between the first surface and the second surface. The first patterned conductive layer is disposed on the first surface. The second patterned conductive layer is disposed on the second surface. The 3D-printing conductive wire is disposed on the third surface and connected between the first patterned conductive layer and the second patterned conductive layer.

Abstract: The present disclosure provides a method of manufacturing a structure. The method comprises: providing a substrate; forming an interconnect layer over the substrate; forming a plurality of conductive pads over the interconnect layer; forming conductive pillars over the interconnect layer; disposing a first semiconductor die over the conductive pads, the semiconductor die being spaced apart from the conductive pillars; and bonding a second semiconductor die with the conductive pillars.

Abstract: Semiconductor chips are provided. A semiconductor chip includes a peripheral circuit region on a substrate. The semiconductor chip includes a semiconductor layer on the peripheral circuit region. The semiconductor chip includes a cell region on the semiconductor layer. Moreover, the semiconductor chip includes a layer/connector that is adjacent the semiconductor layer. Methods of manufacturing semiconductor chips are also provided.

Abstract: Present embodiments provide for a complementary nanowire semiconductor device and fabrication method thereof.

Abstract: A display device includes a first substrate including a first area and a second area, light emitting elements arranged in the first area, connecting pads arranged in the second area, a thin film encapsulation layer arranged on the light emitting elements, a second substrate including a third area and a fourth area, sensing pads arranged in the fourth area, a touch sensor layer including sensing electrodes arranged in the third area and sensing lines connected between the sensing electrodes and the sensing pads, an interlayer arranged between the thin film encapsulation layer and the touch sensor layer, and a conductive member connected between the connecting pads and the sensing pads.

Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein first and second interfaces of a free layer (FL) with a first metal oxide (Hk enhancing layer) and second metal oxide (tunnel barrier), respectively, produce perpendicular magnetic anisotropy (PMA) to increase thermal stability. In some embodiments, metal clusters are formed in the FL and are subsequently partially or fully oxidized by scavenging oxygen to generate additional FL/oxide interfaces that enhance PMA, provide an acceptable resistance x area (RA) value, and preserve the magnetoresistive ratio. In other embodiments, a continuous or discontinuous metal (M) or MQ alloy layer within the FL reacts with scavenged oxygen to form a partially oxidized metal or alloy layer that enhances PMA and maintains acceptable RA. M is one of Mg, Al, B, Ca, Ba, Sr, Ta, Si, Mn, Ti, Zr, or Hf, and Q is a transition metal, B, C, or Al.

Abstract: Methods of forming self-aligned cuts and structures formed with self-aligned cuts. A dielectric layer is formed on a metal hardmask layer, and a mandrel is formed on the dielectric layer. A cut is formed that extends through the dielectric layer to the metal hardmask layer. A section of a metal layer is formed on an area of the metal hardmask layer exposed by the cut in the dielectric layer. After the metal layer is formed, a spacer is formed on a vertical sidewall of the mandrel.

Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity ??100 Ohm.cm, a front surface and a rear surface, at least one LDMOS transistor in the semiconductor substrate, and a RESURF structure. The RESURF structure includes a doped buried layer arranged in the semiconductor substrate, spaced at a distance from the front surface and the rear surface, and coupled with at least one of a channel region and a body contact region of the LDMOS transistor.

Abstract: Disclosed is a display device including a data distribution circuit with enhanced electrical characteristic. The display device includes a plurality of demultiplexing circuits including a gap area which is provided between two transistors, which are adjacent to each other along a first horizontal axis direction, of first to nth transistors and provided in a non-rectilinear shape along a second horizontal axis direction. Here, the gap area may have a zigzag shape along the second horizontal axis direction.

Abstract: A semiconductor structure, such as a microchip that includes a finFET, includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed only upon the sidewalls of the fins.