Patents Examined by Yosef Gebreyesus
  • Patent number: 10249607
    Abstract: An integrated circuit includes a stacked NPN having an upper NPN connected to a lower NPN. The upper NPN includes an upper collector, an upper base, and an upper emitter. The lower NPN includes a lower collector, a lower base, and a lower emitter. The upper collector includes collector segments on opposite sides of the lower emitter. The collector segments are laterally separated by collector separators which are aligned to orientation directions in the collector segments. The upper collector does not have collector separators across the orientation directions.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: April 2, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Henry Litzmann Edwards, Akram Ali Salman
  • Patent number: 10236256
    Abstract: Methods of forming self-aligned cuts and structures formed with self-aligned cuts. A dielectric layer is formed on a metal hardmask layer, and a mandrel is formed on the dielectric layer. A cut is formed that extends through the dielectric layer to the metal hardmask layer. A section of a metal layer is formed on an area of the metal hardmask layer exposed by the cut in the dielectric layer. After the metal layer is formed, a spacer is formed on a vertical sidewall of the mandrel.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Xunyuan Zhang, Shao Beng Law
  • Patent number: 10233388
    Abstract: A lighting device includes a radiation source that emits primary radiation in the wavelength range of 300 nm to 570 nm, a first phosphor arranged in a beam path of the primary radiation source that converts at least part of the primary radiation into secondary radiation in an orange to red wavelength range of 570 nm to 800 nm, and filter particles arranged in a beam path of the secondary radiation that absorb at least part of the secondary radiation.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: March 19, 2019
    Assignee: OSRAM Opto Semiconductors GmbH
    Inventors: Rebecca Römer, Stefan Lange, Dominik Eisert
  • Patent number: 10236213
    Abstract: A gate cut structure for finFETs, and a related method, are disclosed. The gate cut structure separates and electrically isolates an end of a first metal gate conductor of a first finFET from an end of a second metal gate conductor of a second finFET. The gate cut structure includes a body contacting the end of the first and second metal gate conductors. A liner spacer separates a lower portion of the body from an interlayer dielectric (ILD), and an upper portion of the body contacts the ILD. During formation, the liner spacer allows for a larger gate cut opening to be used to allow quality cleaning of the gate cut opening, but also reduction in size of the spacing between metal gate conductor ends of the finFETs. In one example, the body may have a lower portion having a width less than an upper portion thereof.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: March 19, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Shesh M. Pandey, Jiehui Shu, Hui Zang, Laertis Economikos
  • Patent number: 10217775
    Abstract: A display substrate, a manufacturing method thereof, and a display device are disclosed. The display substrate includes a display region and a peripheral region, a display device including the display substrate further includes a gate driving circuit, the gate driving circuit includes a capacitor (C), the capacitor (C) includes a first electrode and a second electrode with an electrical insulation layer provided therebetween. The first electrode and the second electrode are remaining portions of films for forming conductive layers in the display region left in the peripheral region, and the electrical insulation layer is a remaining portion of a film for forming an insulation layer in the display region left in the peripheral region.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: February 26, 2019
    Assignees: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Shijun Wang, Wenbo Jiang, Zhenhua Lv, Zhiying Bao
  • Patent number: 10217906
    Abstract: A light-emitting device includes a semiconductor structure including a first semiconductor layer, a second semiconductor layer, and an active layer formed between the first semiconductor layer and the second semiconductor layer; a surrounding part surrounding the semiconductor structure and exposing a surface of the first semiconductor layer; a first insulating structure formed on the semiconductor structure, including a plurality of protrusions covering the surface of the first semiconductor layer and a plurality of recesses exposing the surface of the first semiconductor layer; a first contact portion formed on the surrounding part and contacting the surface of the first semiconductor layer by the plurality of recesses; a first pad formed on the semiconductor structure; and a second pad formed on the semiconductor structure.
    Type: Grant
    Filed: January 25, 2018
    Date of Patent: February 26, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Chao-Hsing Chen, Jia-Kuen Wang, Tzu-Yao Tseng, Wen-Hung Chuang, Cheng-Lin Lu
  • Patent number: 10211203
    Abstract: A method for fabrication a field-effect-transistor includes forming a plurality of fin structures on a substrate, forming a gate structure across each fin structure and covering a portion of top and sidewall surfaces of the fin structure, forming a first doped layer, made of a first semiconductor material and doped with first doping ions, in each fin structure on one side of the corresponding gate structure, and forming a second doped layer, made of a second semiconductor material, doped with second doping ions, and having doping properties different from the first doped layer, in each fin structure on another side of the corresponding gate structure.
    Type: Grant
    Filed: April 3, 2017
    Date of Patent: February 19, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventors: Xi Lin, Yi Hua Shen, Jian Pan
  • Patent number: 10211171
    Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.
    Type: Grant
    Filed: September 14, 2017
    Date of Patent: February 19, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Kai Liu, Yaojian Lin
  • Patent number: 10199222
    Abstract: The present document discloses a semiconductor device structure (1) comprising a SiC substrate (11), an Inx1Aly1Ga1-x1-y1N buffer layer (13), wherein x1=0-1, y1=0-1 and x1+y1=1, and an Inx2Aly2Ga1-x2-y2N nucleation layer (12), wherein x2=0-1, y2=0-1 and x2+y2=1, sandwiched between the SiC substrate (11) and the buffer layer (13). The buffer layer (13) presents a rocking curve with a (102) peak having a FWHM below 250 arcsec, and the nucleation layer (12) presents a rocking curve with a (105) peak having a FWHM below 200 arcsec, as determined by X-ray Diffraction (XRD). Methods of making such a semiconductor device structure are disclosed.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: February 5, 2019
    Assignee: SWEGAN AB
    Inventors: Erik Janzén, Jr-Tai Chen
  • Patent number: 10199236
    Abstract: A thin film transistor, a manufacturing method thereof, and a method for manufacturing an array substrate are provided. The method for manufacturing the thin film transistor includes: forming an active layer film on a base; and forming a source electrode and a drain electrode of the thin film transistor using a conductive photoresist.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: February 5, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Dezhi Xu, Xianxue Duan, Kui Gong
  • Patent number: 10199546
    Abstract: A micro-transfer color-filter device comprises a color filter, an electrical conductor disposed in contact with the color filter, and at least a portion of a color-filter tether attached to the color filter or structures formed in contact with the color filter. In certain embodiments, a color filter is a variable color filter electrically controlled through one or more electrodes and can be responsive to heat, electrical current, or an electrical field to modify its optical properties, such as color, transparency, absorption, or reflection. In certain embodiments, A color-filter device includes connection posts and can be provided in or on a source wafer suitable for micro-transfer printing. In some embodiments, a color-filter device is disposed on a device substrate and can include a control circuit for controlling the color filter. An array of micro-transfer color-filter devices can be disposed on a display substrate in order to form a display.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: February 5, 2019
    Assignee: X-Celeprint Limited
    Inventors: Ronald S. Cok, Christopher Andrew Bower, Robert R. Rotzoll, Mark Willner
  • Patent number: 10199316
    Abstract: A semiconductor device has a first semiconductor wafer. The first semiconductor wafer is singulated to provide a first wafer section including at least one first semiconductor die or a plurality of first semiconductor die. The first wafer section is a fractional portion of the first semiconductor wafer. An edge support structure is formed around the first wafer section. A second wafer section includes at least one second semiconductor die. The second wafer section can be an entire second semiconductor wafer. The first semiconductor die is a first type of semiconductor device and the second semiconductor die is a second type of semiconductor device. An alignment opening is formed through the first wafer section and second wafer section with a light source projected through the opening. The first wafer section is bonded to the second wafer section with the first semiconductor die aligned with the second semiconductor die.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: February 5, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney
  • Patent number: 10193062
    Abstract: A magnetic tunnel junction (MTJ) is disclosed wherein first and second interfaces of a free layer (FL) with a first metal oxide (Hk enhancing layer) and second metal oxide (tunnel barrier), respectively, produce perpendicular magnetic anisotropy (PMA) to increase thermal stability. In some embodiments, a continuous or discontinuous metal (M) or MQ alloy layer within the FL reacts with scavenged oxygen to form a partially oxidized metal or alloy layer that enhances PMA and maintains acceptable RA. M is one of Mg, Al, B, Ca, Ba, Sr, Ta, Si, Mn, Ti, Zr, or Hf, and Q is a transition metal, B, C, or Al. Methods are also provided for forming composite free layers where interfacial perpendicular anisotropy is generated therein by contact of the free layer with oxidized materials.
    Type: Grant
    Filed: May 7, 2018
    Date of Patent: January 29, 2019
    Assignee: Headway Technologies, Inc.
    Inventors: Jodi Mari Iwata, Guenole Jan, Ru-Ying Tong, Po-Kang Wang
  • Patent number: 10186487
    Abstract: A semiconductor device includes a first chip having a through via, a second chip having a first terminal that is electrically connected to the through via, and a substrate having a second terminal disposed on a first surface thereof and electrically connected to the first terminal. When viewed along a straight line that intersects a center axis that is perpendicular to the first surface and intersects a center point of the substrate, the first terminal is disposed further towards the center axis than the second terminal and the through via is disposed further towards the center axis than the first terminal.
    Type: Grant
    Filed: August 28, 2017
    Date of Patent: January 22, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazushige Kawasaki, Mikihiko Ito, Masaru Koyanagi
  • Patent number: 10186395
    Abstract: A horizontal multilayer junction-edge field emitter includes a plurality of vertically-stacked multilayer structures separated by isolation layers. Each multilayer structure is configured to produce a 2-dimensional electron gas at a junction between two layers within the structure. The emitter also includes an exposed surface intersecting the 2-dimensional electron gas of each of the plurality of vertically-stacked multilayer structures to form a plurality of effectively one-dimensional horizontal line sources of electron emission.
    Type: Grant
    Filed: October 13, 2017
    Date of Patent: January 22, 2019
    Assignee: Elwha LLC
    Inventors: Roderick A. Hyde, Jordin T. Kare, Tony S. Pan, Lowell L. Wood, Jr.
  • Patent number: 10181480
    Abstract: A thin film transistor “TFT”) substrate includes a substrate, an active layer over the substrate, and first and second TFTs over the substrate. The active layer includes: a first drain region, a first channel region and a first source region, which function as a drain, a channel and a source of the first TFT: a first lightly doped region between the first drain region and the first channel region: a second lightly doped region between the first channel region and the first source region: and a second drain region, a second channel region and a second source region, which function as a drain, a channel and a source of the second TFT. An impurity concentration at the second drain or source region is lower than an impurity concentration at the first drain or source region and higher than an impurity concentration at the first or second channel region.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: January 15, 2019
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sangho Park, Gyungsoon Park, Heerim Song, Donghwan Shim, Jungkyu Lee, Seunghwan Cho, Jonghyun Choi
  • Patent number: 10177124
    Abstract: The present invention discloses a flexible micro-LED display module, comprising: a flexible substrate, a substrate protection layer, a lattice matching layer, an LED array, a transparent conductive substrate, and a light conversion layer. The light conversion layer is constituted by a plurality of red light conversion units, a plurality of green light conversion units, and a plurality of blue light conversion units, such that one pixel is formed by one red light conversion unit, one green light conversion unit, one blue light conversion unit, and several light-emitting elements. In the case of some light-emitting elements failing to radiate light normally, the defective pixel correction circuit is used to apply luminous intensity adjusting process to other light-emitting elements working normally, so as to make the flexible micro-LED display module able to display video or images with the lowest number of defective pixels capable of meeting the requirements of pixel standards.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: January 8, 2019
    Assignee: FLEX TEK CO., LTD.
    Inventors: Yao-Hsien Huang, Sheng-Hui Chen
  • Patent number: 10177224
    Abstract: A semiconductor device includes a stack structure located on a substrate and includes a first region, in which sacrificial layers and insulating layers are alternately stacked, and a second region, in which conductive layers and insulating layers are alternately stacked. The stack structure also includes a first slit insulating layer located at a boundary between the first region and the second region, wherein the first slit insulating layer penetrates the stack structure and extends in one direction. The stack structure further includes a plurality of slit insulating patterns located in the second region, wherein the plurality of slit insulating patterns penetrate the stack structure and are arranged along the one direction. At least one conductive layer among the conductive layers is bent between the first slit insulating layer and the slit insulating patterns.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: January 8, 2019
    Assignee: SK hynix Inc.
    Inventors: Hae Chan Park, Jae Taek Kim
  • Patent number: 10170676
    Abstract: An embodiment relates to a light emitting device package and a lighting apparatus having the same. According to the embodiment, a light emitting device package includes a first lead frame; a second lead frame spaced apart from the first lead frame; a body coupled to the first lead frame and the second lead frame and includes a first cavity which exposes a portion of the upper surface of the first lead frame, a second cavity which exposes a portion of the upper surface of the second lead frame, and a spacer which is disposed between the first lead frame and the second frame; at least one light emitting device disposed in the first cavity; and a protection device disposed in the second cavity. The second cavity is disposed on a first inside surface of the first cavity and the first inside surface is connected to an upper surface of the spacer, and an area of a bottom surface of the first cavity is equal to or less than 40% of entire area of the body.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: January 1, 2019
    Assignee: LG Innotek Co., Ltd.
    Inventors: Chang Man Lim, Won Jung Kim, Hyoung jin Kim, Bong Kul Min, Ho Young Chung
  • Patent number: 10170474
    Abstract: A semiconductor structure, such as a microchip that includes a finFET, includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed upon the sidewalls of the fins.
    Type: Grant
    Filed: January 5, 2018
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Sami Rosenblatt, Rasit O. Topaloglu