Patents Examined by Yosef Gebreyesus
  • Patent number: 10340443
    Abstract: An embodiment includes an apparatus comprising: first and second electrodes on a substrate; a perpendicular magnetic tunnel junction (pMTJ), between the first and second electrodes, comprising a dielectric layer between a fixed layer and a free layer; and an additional dielectric layer directly contacting first and second metal layers; wherein (a) the first metal layer includes an active metal and the second metal includes an inert metal, and (b) the second metal layer directly contacts the free layer. Other embodiments are described herein.
    Type: Grant
    Filed: June 26, 2015
    Date of Patent: July 2, 2019
    Assignee: Intel Corporation
    Inventors: Brian S. Doyle, Kaan Oguz, Kevin P. O'Brien, David L. Kencke, Elijah V. Karpov, Charles C. Kuo, Mark L. Doczy, Satyarth Suri, Robert S. Chau, Niloy Mukherjee, Prashant Majhi
  • Patent number: 10340346
    Abstract: A semiconductor device includes a drain layer, a drift layer, a base region, a source region, trenches, base contact region, gate regions, and field plate electrodes. The drain layer extends in a first and a second direction. The drift layer is on the drain layer. The base region is on the drift layer. The source region is on the base region. The trenches are in an array and each trench reaches the drift layer from the source region. The base contact region is along the second direction in a region in which the trenches do not contiguously exist along the second direction and electrically connects the source region to the base region. Each gate regions is along an inner wall of the trenches. Each field plate electrodes is in an inside of the gate regions and is longer than the gate regions in the third direction.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: July 2, 2019
    Assignees: Kabushiki Kaisha Toshiba, Toshiba Electronic Devices & Storage Corporation
    Inventors: Hiroaki Katou, Kenya Kobayashi
  • Patent number: 10340334
    Abstract: In an embodiment, a semiconductor device includes a semiconductor substrate having a bulk resistivity ??100 Ohm.cm, a front surface and a rear surface. An LDMOS transistor is arranged in the semiconductor substrate. A RESURF structure including a doped buried layer is arranged in the semiconductor substrate. The LDMOS transistor includes a body contact region doped with a first conductivity type, and a source region disposed in the body contact region and doped with a second conductivity type opposite the first conductivity type. The source region includes a first well and a second well of the same second conductivity type. The first well is more highly doped than the second well. The first well extends from inside the body contact region to outside of a lateral extent of the body contact region in a direction towards a source side of a gate of the LDMOS transistor.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: July 2, 2019
    Assignee: Infineon Technologies AG
    Inventors: Albert Birner, Helmut Brech, Matthias Zigldrum, Michaela Braun, Christian Eckl
  • Patent number: 10340422
    Abstract: A display device and a display panel are provided. The display panel includes an array panel and a plurality of display devices. The display device includes a display device main body and a magnetic member disposed on the display device main body. The display device can be transferred to the array panel under a force of a magnetic field outside of the display device. The present disclosure can efficiently transfer the display devices to the array panel.
    Type: Grant
    Filed: November 22, 2017
    Date of Patent: July 2, 2019
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Lixuan Chen
  • Patent number: 10340296
    Abstract: An array substrate and a display device are provided for solving a problem of drift of an I-V curve of a thin film transistor because the oxide active layer is irradiated with light in the prior art. The array substrate includes a plurality of thin film transistors arranged in an array, wherein, each of the thin film transistors includes an oxide active layer, and the array substrate further includes a light absorption layer provided above the oxide active layer, the light absorption layer is used for absorbing light irradiated thereon, and an orthographic projection of the light absorption layer on the oxide active layer at least partly covers an active region of the oxide active layer.
    Type: Grant
    Filed: January 22, 2016
    Date of Patent: July 2, 2019
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Guanghui Liu, Bin Zhou
  • Patent number: 10319687
    Abstract: A soluble sensor is provided. The soluble sensor includes a soluble handle substrate and a layer of semiconductor material that is disposed on the soluble handle substrate. The layer of semiconductor material includes a plurality of semiconductor devices interconnected to perform a sensing function.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: June 11, 2019
    Assignee: Honeywell International Inc.
    Inventor: Steven Tin
  • Patent number: 10319808
    Abstract: A semiconductor device is provided, including a semiconductor substrate; a first conductivity type drift region provided inside the semiconductor substrate; a plurality of gate trench portions provided extending from an upper surface of the semiconductor substrate and reaching the drift region; a dummy trench portion provided between two gate trench portions and provided extending from the upper surface of the semiconductor substrate and reaching the drift region; a second conductivity type base region provided: in a region of the semiconductor substrate adjacent to any of the gate trench portions; and between the upper surface of the semiconductor substrate and the drift region; and a second conductivity type first well region provided: in a region of the semiconductor substrate adjacent to the dummy trench portion; and reaching a position deeper than a lower end of the dummy trench portion; and having a doping concentration higher than that of the base region.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: June 11, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Tatsuya Naito
  • Patent number: 10312301
    Abstract: A display device includes a first substrate including a first area and a second area, light emitting elements arranged in the first area, connecting pads arranged in the second area, a thin film encapsulation layer arranged on the light emitting elements, a second substrate including a third area and a fourth area, sensing pads arranged in the fourth area, a touch sensor layer including sensing electrodes arranged in the third area and sensing lines connected between the sensing electrodes and the sensing pads, an interlayer arranged between the thin film encapsulation layer and the touch sensor layer, and a conductive member connected between the connecting pads and the sensing pads.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: June 4, 2019
    Assignee: Samsung Display Co., Ltd.
    Inventors: Su Hyuk Choi, Jin Woo Park, Ho Youn Kim, Hyun Chul Oh, Ung Soo Lee, Jun Young Lee, Hyun Soo Jung
  • Patent number: 10297616
    Abstract: A display panel includes a gate integrated circuit, a number of scan lines extending from the gate integrated circuit for transmitting scan signals, a source integrated circuit, a number of data lines extending from the source integrated circuit for transmitting data signals, a number of pixel electrodes for receiving the scan signals and the data signals, and a number of transistors each electrically coupled to a corresponding scan line, a corresponding data line, and a corresponding pixel electrode. The transistors each include a gate electrode, a source electrode, and a drain electrode. The drain electrode includes an overlapping portion overlapping with the gate electrode. The gate integrated circuit transmits the scan signals along the scan lines. A size of the overlapping portion increases along a transmitting direction of the scan signal along the scan line.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: May 21, 2019
    Assignee: Century Technology (Shenzhen) Corporation Limited
    Inventors: Ming-Tsung Wang, Chih-Chung Liu, Yi-Hsiu Cheng, Wen-Qiang Yu
  • Patent number: 10290624
    Abstract: Disclosed is an ESD protection device, comprising: a semiconductor substrate; a semiconductor buried layer located in the semiconductor substrate; an epitaxial semiconductor layer located on the semiconductor substrate and comprising a first doped region and a second doped region, wherein the semiconductor substrate and the first doped region are of a first doping type, the semiconductor buried layer, the epitaxial semiconductor layer and the second doped region are of a second doping type, the first doping type and the second doping type are opposite to each other, and the first doped region forms a plurality of interfaces with the epitaxial semiconductor layer. The disclosure improves protection performance and maximum current bearing capacity without increasing parasitic capacitance of the ESD protection device.
    Type: Grant
    Filed: October 11, 2017
    Date of Patent: May 14, 2019
    Assignee: Silergy Semiconductor Technology (Hangzhou) Ltd.
    Inventors: Fei Yao, Shijun Wang, Dengping Yin
  • Patent number: 10290617
    Abstract: An electroluminescent light source including light-emitting diodes arranged on a substrate made of silicon. The light source integrates an electronic circuit performing a function that is necessary for controlling the light-emitting diodes.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: May 14, 2019
    Assignee: VALEO VISION
    Inventors: Lothar Seif, Zdravko Zojceski, Vanessa Sanchez, Gilles Le Calvez
  • Patent number: 10290649
    Abstract: According to one embodiment, a semiconductor device includes a foundation layer, a stacked body provided above the foundation layer, a columnar portion, a hole, and a sealing film. The stacked body includes a plurality of conductive layers stacked with an air gap interposed. The columnar portion includes a semiconductor body. The semiconductor body extends in a stacking direction of the stacked body through the stacked body and contacts the foundation layer. The hole extends in the stacking direction through the stacked body and forms a cavity communicating with the air gap. The sealing film plugs an upper end of the hole forming the cavity.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: May 14, 2019
    Assignee: Toshiba Memory Corporation
    Inventor: Koichi Matsuno
  • Patent number: 10283642
    Abstract: Manufacturing techniques and related semiconductor devices are disclosed in which the channel region of analog transistors and/or transistors operated at higher supply voltages may be formed on the basis of a very thin semiconductor layer in an SOI configuration by incorporating a counter-doped region into the channel region at the source side of the transistor. The counter-doped region may be inserted prior to forming the gate electrode structure. With this asymmetric dopant profile in the channel region, superior transistor performance may be obtained, thereby obtaining a performance gain for transistors formed on the basis of a thin semiconductor base material required for the formation of sophisticated fully depleted transistor elements.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: May 7, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Alban Zaka, Ignasi Cortes Mayol, Tom Herrmann, El Mehdi Bazizi, Luca Pirro
  • Patent number: 10276719
    Abstract: In a method of manufacturing a semiconductor device, an opening is formed in an interlayer dielectric layer such that a source/drain region is exposed in the opening. A first semiconductor layer is formed to fully cover the exposed source/drain region within the opening. A heating process is performed to make an upper surface of the first semiconductor layer substantially flat. A conductive contact layer is formed over the first semiconductor layer.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: April 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Blandine Duriez, Gerben Doornbos, Mark Van Dal, Martin Christopher Holland
  • Patent number: 10276570
    Abstract: A semiconductor device, including first and second fin patterns separated by a first trench; a gate electrode intersecting the first and second fin patterns; and a contact on at least one side of the gate electrode, the contact contacting the first fin pattern, the contact having a bottom surface that does not contact the second fin pattern, a height from a bottom of the first trench to a topmost end of the first fin pattern in a region in which the contact intersects the first fin pattern being a first height, and a height from the bottom of the first trench to a topmost end of the second fin pattern in a region in which an extension line of the contact extending along a direction in which the gate electrode extends intersects the second fin pattern being a second height, the first height being smaller than the second height.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: April 30, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Gun You, Hyung-Jong Lee, Sung-Min Kim, Chong-Kwang Chang
  • Patent number: 10269565
    Abstract: The present document discloses a semiconductor device structure (1) comprising a SiC substrate (11), an Inx1Aly1Ga1-x1-y1N buffer layer (13), wherein x1=0-1, y1=0-1 and x1+y1=1, and an Inx2Aly2Ga1-x2-y2N nucleation layer (12), wherein x2=0-1, y2=0-1 and x2+y2=1, sandwiched between the SiC substrate (11) and the buffer layer (13). The buffer layer (13) presents a rocking curve with a (102) peak having a FWHM below 250 arcsec, and the nucleation layer (12) presents a rocking curve with a (105) peak having a FWHM below 200 arcsec, as determined by X-ray Diffraction (XRD). Methods of making such a semiconductor device structure are disclosed.
    Type: Grant
    Filed: January 9, 2015
    Date of Patent: April 23, 2019
    Assignee: SWEGAN AB
    Inventors: Erik Janzén, Jr-Tai Chen
  • Patent number: 10263019
    Abstract: A flexible panel includes a substrate, a first insulating layer, a second insulating layer, a sacrificial layer, and a metal wiring layer. The substrate has an active area, a peripheral area, and an intermediate area. The first insulating layer is in the three areas of the substrate, and the first insulating layer in the intermediate area has a first pattern. The second insulating layer is on the first insulating layer. The second insulating layer in the intermediate area has a first opening extending along a first direction, so that the second insulating layer does not cover the first pattern of the first insulating layer. The sacrificial layer is between the first insulating layer and the second insulating layer in the intermediate area, and does not cover the first pattern of the first insulating layer. The metal wiring layer extends between the active area and the peripheral area.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: April 16, 2019
    Assignee: AU OPTRONICS CORPORATION
    Inventors: Pei-Yun Wang, Cheng-Wei Jiang, Ting-Yu Hsu, Ya-Qin Huang, Hsiang-Yun Hsiao, Chia-Kai Chen
  • Patent number: 10263102
    Abstract: An object of the present invention is to provide a semiconductor device capable of preventing an occurrence of oscillation of voltage and current and a method of manufacturing the same. A semiconductor device according to the present invention includes an n type silicon substrate and a first n type buffer layer formed in a back surface of the n type silicon substrate and having a plurality of peaks of concentration of protons whose depths from the back surface are different from each other. In the first n type buffer layer, a concentration gradient of the protons from the peak located in a position closer to the back surface toward the surface of the n type silicon substrate is smaller than a concentration gradient of the protons from the peak located in a position farther away from the back surface toward the surface.
    Type: Grant
    Filed: February 16, 2018
    Date of Patent: April 16, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Kenji Suzuki, Mitsuru Kaneda, Koichi Nishi, Katsumi Nakamura
  • Patent number: 10256159
    Abstract: A method is presented for forming a semiconductor structure. The method includes forming a silicon (Si) channel for a first device, forming a first interfacial layer over the Si channel, forming a silicon-germanium (SiGe) channel for a second device, forming a second interfacial layer over the SiGe channel, and selectively removing germanium oxide (GeOX) from the second interfacial layer by applying a combination of hydrogen (H2) and hydrogen chloride (HCl). The second interfacial is silicon germanium oxide (SiGeOX) and removal of the GeOX results in formation of a pure silicon dioxide (SiO2) layer.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: April 9, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Hemanth Jagannathan, ChoongHyun Lee, Shogo Mochizuki
  • Patent number: 10254243
    Abstract: The present invention concerns an ion sensor based on differential measurement, that by means of at least two ion-sensitive field-effect transistors, compares the concentration of certain ions in a solution to be measured with the concentration of certain ions in a reference solution contained in a micro-reservoir with a micro-channel. To do this, the micro-reservoir and the micro-channel cover at least the gate of one of the ion-sensitive field-effect transistors and make up a unit partially filled with a porous material that covers the entirety of the aforementioned gate and at least the base of the micro-channel.
    Type: Grant
    Filed: July 12, 2016
    Date of Patent: April 9, 2019
    Assignee: CONSEJO SUPERIOR DE INVESTIGACIONES CIENTIFICAS (CSIC)
    Inventors: Antonio Baldi Coll, César Fernández Sánchez, Alfredo Cadarso Busto