Abstract: A light emitting device includes a substrate; a plurality of light emitting cells disposed on the substrate to be spaced apart from one another, the light emitting cell having a via hole passing through the second conductive type semiconductor layer, the active layer and a part of the first conductive type semiconductor layer; a first electrode layer electrically connected to the first conductive type semiconductor layer at a bottom of the via hole; a second electrode layer disposed on the second conductive type semiconductor layer; and a first passivation layer, electrically separating the first electrode layer from the second electrode layer, wherein the first electrode layer of one light emitting cell is electrically connected to the second electrode layer of another light emitting cell adjacent to the one light emitting cell.

Abstract: Monolithic microwave integrated circuits are provided that include a substrate having a transistor and at least one additional circuit formed thereon. The transistor includes a drain contact extending in a first direction, a source contact extending in the first direction in parallel to the drain contact, a gate finger extending in the first direction between the source contact and the drain contact and a gate jumper extending in the first direction. The gate jumper conductively connects to the gate finger at two or more locations that are spaced apart from each other along the first direction.

Abstract: A semiconductor chip includes a substrate, an electrode pad formed on the substrate, an insulating layer covering the substrate and the electrode pad, and having an opening exposing a portion of a surface of the electrode pad, a first conductive layer formed on the exposed portion of the surface of the electrode pad and extending to a surface of the insulating layer, and a second conductive layer formed on the first conductive layer, covering the first conductive layer in a plan view, and having an outer edge portion which is located further out than an outer edge of the first conductive layer in a plan view. The outer edge portion of the second conductive layer has at least one curved portion. At least one portion of the curved portion is located between the outer edge of the first conductive layer and an outer edge of the second conductive layer in a plan view.

Abstract: Disclosed herein is a 3D memory with a select transistor, and method for fabricating the same. The select transistor may have a conductive floating gate, a conductive control gate, a first dielectric between the conductive floating gate and the conductive control gate, and a second dielectric between a body and the conductive floating gate. In one aspect, a uniform gate dielectric is formed using lateral epitaxial growth in a recess adjacent a crystalline semiconductor select transistor body, followed by forming the gate dielectric from the epitaxial growth. Techniques help to prevent, or at least reduce, a leakage current between the select transistor control gate and the select transistor body and/or the semiconductor substrate below the select transistor. Therefore, select transistors having a substantially uniform threshold voltage, on current, and S-factor are achieved. Also, select transistors have a high on-current and a steep sub-threshold slope.

Abstract: The present disclosure relates to an integrated circuit, which includes a semiconductor substrate and an interconnect structure disposed over the semiconductor substrate. The interconnect structure includes a lower metal layer, an intermediate metal layer disposed over the lower metal layer, and an upper metal layer disposed over the intermediate metal layer. An upper surface of the lower metal layer and a lower surface of the intermediate metal layer are spaced vertically apart by a first distance. A resistive random access memory (RRAM) cell is arranged between the lower metal layer and the upper metal layer. The RRAM cell includes a bottom electrode and a top electrode which are separated by a data storage layer having a variable resistance. The data storage layer vertically spans a second distance that is greater than the first distance.

Abstract: A multi-tier memory device includes a first tier structure overlying a substrate and containing a first alternating stack of first insulating layers and first electrically conductive layers, and first memory stack structures each including a first memory film and a first vertical semiconductor channel, a source line overlying the first tier structure, and a second tier structure overlying the source line and containing a second alternating stack of second insulating layers and second electrically conductive layers, and second memory stack structures each including a second memory film and a second vertical semiconductor channel.

Abstract: The present disclosure relates to a flash memory cell. In some embodiments, the flash memory cell has a control gate arranged over a substrate, and a select gate separated from the substrate by a gate dielectric layer. A charge trapping layer has a first portion disposed between the select gate and the control gate, and a second portion arranged under the control gate. A first control gate spacer is arranged on the second portion of the charge trapping layer. A second control gate spacer is arranged on the second portion of the charge trapping layer and is separated from the control gate by the first control gate spacer.

Abstract: An area of a region arranged on one side out of a display region in a direction in which scanning signal lines extend is reduced. A display apparatus includes: a partial circuit; a plurality of scanning signal lines; and a plurality of scanning signal connection wirings for connecting the partial circuit and each of the plurality of scanning signal lines. Each of the plurality of scanning signal lines extends in an X-axis direction, and is arranged with a pitch in a Y-axis direction. A plurality of ends respectively included in the plurality of scanning signal connection wirings are connected to the partial circuit, and are arranged in the Y-axis direction. A distance in the Y-axis direction between the respective centers of the two ends adjacent to each other is narrower than the pitch.

Abstract: A semiconductor device includes first and second semiconductor components mounted on an interposer mounted on a wiring substrate, and electrically connected to each other via the interposer. Also, a plurality of wiring layers of the interposer include first, second and third wiring layers which are stacked in order from a main surface side to be a reference. In addition, in a first region of the interposer sandwiched between the first semiconductor component and the second semiconductor component, a ratio of a reference potential wiring in the third wiring layer is higher than a ratio of a reference potential wiring in the first wiring layer. Further, in the first region, a ratio of a signal wiring in the first wiring layer is higher than a ratio of a signal wiring in the third wiring layer.

Abstract: Some embodiments of the present disclosure relate to a method. In this method, a semiconductor substrate, which has an active region disposed in the semiconductor substrate, is received. A shallow trench isolation (STI) structure is formed to laterally surround the active region. An upper surface of the active region bounded by the STI structure is recessed to below an upper surface of the STI structure. The recessed upper surface extends continuously between inner sidewalls of the STI structure and leaves upper portions of the inner sidewalls of the STI structure exposed. A semiconductor layer is epitaxially grown on the recessed surface of the active region between the inner sidewalls of the STI structure. A gate dielectric is formed over the epitaxially-grown semiconductor layer. A conductive gate electrode is formed over the gate dielectric.

Abstract: There is provided a photodiode array. The photodiode array includes a substrate that has an optical interface surface arranged for accepting external input radiation into the substrate. A plurality of photodiodes are disposed at a substrate surface opposite the optical interface surface of the substrate. Each photodiode in the plurality of photodiodes includes a photodiode material that generates light into the substrate as a result of external input radiation absorption by the photodiode. There is aperiodic photodiode placement along at least one direction of the array.

Abstract: A micromechanical structure is described, including: at least one elastically deformable first area, which includes a defined piezoelectrically doped second area, at least in sections; at least one fourth area, into which the electrical charges generated in the second area may be conducted; and at least one third area connected electrically to the second and fourth area, in which an electrical current flowing through is convertible into thermal energy.

Abstract: A method for forming a microelectromechanical device may provide forming a first layer at least one of in or over a semiconductor carrier; forming a second layer at least one of in or over at least a central region of the first layer, such that a peripheral region of the first layer is at least partially free of the second layer; removing material under at least a central region of the second layer to release at least one of the central region of the second layer or a central region of the first layer; and/or removing material under at least the peripheral region of the first layer to such that the second layer is supported by the semiconductor carrier via the first layer.

Abstract: A method of manufacturing a light emitting device includes providing a light emitting element; and forming a protective film on a surface of the light emitting element, wherein the step of forming the protective film includes: (i) providing first quantity of oxygen at the surface of the light emitting element, (ii) combining a first quantity of a first metal with the first quantity of oxygen, (iii) combining a second quantity of oxygen with the first quantity of metal, (iv) combining a first quantity of a second metal, different from the first metal, with the second quantity of oxygen and first quantity of the first metal, and (v) combining a third quantity of oxygen with the first quantity of the second metal.

Abstract: Techniques for fabricating horizontally aligned nanochannels are provided. In one aspect, a method of forming a device having nanochannels is provided. The method includes: providing a SOI wafer having a SOI layer on a buried insulator; forming at least one nanowire and pads in the SOI layer, wherein the nanowire is attached at opposite ends thereof to the pads, and wherein the nanowire is suspended over the buried insulator; forming a mask over the pads, the mask having a gap therein where the nanowire is exposed between the pads; forming an alternating series of metal layers and insulator layers alongside one another within the gap and surrounding the nanowire; and removing the nanowire to form at least one of the nanochannels in the alternating series of the metal layers and insulator layers. A device having nanochannels is also provided.

Abstract: Embodiments are related to systems and methods for fluidic assembly, and more particularly to systems and methods for assuring deposition of elements in relation to a substrate.

Abstract: In accordance with an example embodiment of the present invention, a device is disclosed. The device comprises: a sensing region comprising an active material and two or more electrodes in electrical contact with the active material; and a switching region providing control over the sensing region, the switching region comprising an active material and two or more electrodes in electrical contact with the active material. The switching region and the sensing region share one electrode, and the switching region and the sensing region share at least part of the active material. A method and apparatus for producing the device are also disclosed.

Abstract: The present invention provides a TFT substrate manufacturing method and a TFT substrate manufactured with the method. The TFT substrate manufacturing method of the present invention uses a photoresist pattern to serve as a shielding mask to allow a metal layer to be directly oxidized, through the anodic oxidation technology, into a gate insulation layer or a passivation layer, and at the same time, forming electrode patterns of gate or source/drain. The entire operation can be conducted in room temperature and is applicable to a flexible substrate that is not resistant to high temperatures without the involvement of expensive high temperature facility, such as chemical vapor deposition, so as to greatly reduce the operation cost of manufacturing a flexible display device. The TFT substrate manufactured with the present invention shows excellent electrical characteristics and is suitable for a flexible display device.

Abstract: A method and system for changing a pressure within at least one enclosure in a MEMS device are disclosed. In a first aspect, the method comprises applying a laser through one of the at least two substrates onto a material which changes the pressure within at least one enclosure when exposed to the laser, wherein the at least one enclosure is formed by the at least two substrates. In a second aspect, the system comprises a MEMS device that includes a first substrate, a second substrate bonded to the first substrate, wherein at least one enclosure is located between the first and the second substrates, a metal layer within one of the first substrate and the second substrate, and a material vertically oriented over the metal layer, wherein when the material is heated the material changes a pressure within the at least one enclosure.

Abstract: An electronic device includes a transducer including a sensing area and a covering structure that covers the transducer. The covering structure includes a shelter portion and defines at least one aperture. The shelter portion covers the sensing area. The aperture includes a first curved surface and a second curved surface farther away from the sensing area than the first curved surface, and a first center of a first curvature of the first curved surface is at a different location than a second center of a second curvature of the second curved surface.