Abstract: Clock timing is extracted from N level, multilevel codes of megabits per second data by determining a baud clock among the N-1 possible clocks synchronized to all the level cross points. A discriminator is used with a clock and if correct information is not obtained, the clock is changed.

Abstract: A multi-edge clock recovery method is provided that may be used with data streams having at least three (3) levels. According to the invention, when each threshold is crossed, it generates data edges for that particular threshold. These data edges latching the polarity of the recoverd clock at the time the corresponding threshold was crossed, thereby indicating the "late" and "early" edge information for that threshold crossing with respect to the falling edge of the recovered clock. Immediately following the decoding of the most recent multi-level symbol, the appropriate threshold for the data transition is determined. The decoded values of the sumbols preceding and following the data edges determine which threshold should be selected for "late" and "early" edge indications. The recorded late/early data edge status for this selected threshold is then used for determining when it is necessary to correct the phase of the recovered clock.

Abstract: In a system where a signal constellation is used for data communications, signal points in the signal constellation are selected to represent incoming data. The signal points, thus selected, are transmitted through a channel. The signal constellation is divided into a plurality of regions each including an equal number of signal points. A coding scheme is employed to ensure that signal points within any one region are selected equiprobably, and the probability of selecting any signal point in one region is different from that in another region.

Abstract: A MODEM has a delay equalizer for receiving a trellis-coded test signal transmitted from an opposite MODEM and compensating for delay distortion of this test signal on the transmission path. The output of this delay equalizer and the input test signal are selectively entered into a demodulator. The output of this demodulator is assigned to predetermined signal point coordinates by a decision circuit. A Viterbi decoder computes a branch metric representing the distance between each assigned point and receive signal point from the output signals of the decision circuit and the demodulator, and figures out the pass metrics of accumulated values based on the branch metrics so computed. A difference signal represents the difference between the maximum and minimum values of the pass metrics from the Viterbi decoder.

Abstract: A mapping technique for an 8D, sixty-four state convolutionally coded 19.2 Kbit/second modem utilizes twenty-nine bits for defining all points of an 8D constellation. The 8D constellation which is mapped is comprised of a desired subset of a concatenation of four 2D constellations, where each 2D constellation has one hundred ninety-two points. The mapping technique generally comprises: dividing each 2D constellation into six different energy groups of thirty-two points each, the concatenation of four groups, one from each 2D constellation, comprising an 8D grouping; choosing five hundred twelve 8D groupings from the possible one thousand two hundred ninety-six (6.sup.

Abstract: Asynchronous DS-1 data is byte synchronized and converted to the SONET VT1.5 format by storing the DS-1 data in a store from which it is read in dependence upon a gapped clock signal which is produced by gapping a first gapped clock signal with a ratio of 208/193, which is the ratio of VT SPE bits per frame to DS-1 bits per frame. The first gapped clock signal is produced by gapping a VT1.5 synchronous clock signal. A frequency difference between the first gapped clock signal and the asynchronous data rate, multiplied in a frequency multiplier by the ratio of 208/193, is monitored by comparing the counts of modulo-208 counters, and, in dependence upon the monitored frequency difference, the gapping of the synchronous clock signal is controlled to achieve positive or negative stuffing and hence to compensate for the frequency difference.

Abstract: An all-digital phase-locked loop (PLL) for synchronizing an output clock signal with a reference clock signal. The PLL has a multiple-tap, digital delay chain in its forward path for delaying the output clock signal, which delay chain is controlled by a digital number stored by a counter in its feedback path. A phase detector in the feedback path provides LEAD and LAG signals, the status of which indicates whether the output clock signal leads or lags the reference signal. In response to the LEAD and LAG signals, a digital sequencer in the feedback path generates the digital number and stores it in the counter. The digital sequencer changes the digital number until the state of the LEAD and LAG signals reverses, and then returns the counter back to its state prior to LEAD and LAG reversal, for synchronism. The digital sequencer also causes a phase reversal of the output signal where the number of delay taps needed for synchronism is large.

Abstract: An improved method for detecting that a facility delay has changed is provided. According to the invention, a facility having a delay that may change is coupled to a transmitter and a receiver. The transmitter is coupled to a first clock that transmits a first signal based on its current reading (the first clock signal) from time to time to the receiver via the facility. The receiver is coupled to a second clock that generates a second signal based on its current reading (the second clock signal) responsive to receiving the first clock signal. In operation, the first clock signal is fed downstream (via the facility having the delay), thereby triggering the second clock signal. The two clock signals are then detected and the difference in the two clock readings computed, thereby forming .DELTA..sub.n. The process is then repeated for successive first and second clock signals, thereby forming .DELTA..sub.n+1. The absolute value of .DELTA..sub.n -.DELTA..sub.

Abstract: The invention provide a digital method of correcting non-linearity in a transmission chain, in which the effects of amplifier non-linearities are compensated by applying predistortion in baseband prior to modulation, with the signal being processed digitally in real time. The invention also provides apparatus for implementing the method. The invention is particularly applicable to radio beams for conveying digital signals.

Abstract: A signal is transmitted to a receiver and is digitalized in signal points (S1). These points are viterbi analyzed in an analyzer with a path memory (PM) having a desired number of states (00, 01, 10, 11) with memory cells (MC). Bit sequences, corresponding to the signal points (S1), are generated and final metric values (m0, m1+g1, m1, m3) for the bit sequences are calculated. In an indicated bit position the best bit sequence, with the smallest final metric value (m2), has a "1", which is the decided bit value. An alternative bit sequence is generated, which is the best bit sequence with the smallest final metric value (m0+g0) under the condition that in the indicated bit position there is bit with the opposite bit value, a "0". The difference between both the final metric values (m0+m0-m2) is a quality factor for the decided bit value "1". The calculation is made in three steps. At a time point metric values (m0, m1, m2, m3) have been calculated for the different states (00, 01, 10, 11).

Abstract: A signal processing method and system in a receiving apparatus including a receiving equalizer circuit are provided for extracting transmission data from a received signal inputted via a transmission path every transmission frame having a predetermined synchronization pattern and transmission data. A phase error is detected from the received signal extracted in synchronism with a sampling signal in the receiving equalizer circuit. The frequency of the sampling signal is controlled until the phase error becomes minimum. In parallel, it is detected whether the frame synchronization pattern is present in the received signal in a predetermined interval or not. When the presence of the frame synchronization pattern is not detected after the phase has been stabilized by frequency control of the sampling signal, the sampling phase of the received signal is judged to be in the quasi-convergence state. Then the frequency of the sampling signal is forcibly changed largely.

Abstract: A method of an apparatus for decision feedback equalization, capable of dealing with time reversal for the transmission characteristic arising in a course of equalization. Without a considerable increase of the number of taps used and the resulting reduction of the response speed. In this apparatus, a number of feedforward taps for providing a forward part and a number of feedback taps for providing a feedback part are controlled according to whether the transmission signal is to be read in a normal time direction or in a reversed time direction; the forward part and the feedback part are added; and the digital transmission signal is reconstructed according to a result of the addition.

Abstract: The decision feedback decoder of the invention receives sequentially sampled values of a signal waveform corresponding to data bits transmitted by a channel. A magnitude comparator compares the sampled values to a threshold and based on each comparison it provides subsequent decisions determining the values of the corresponding data bits. A predetermined number of previous decisions are stored and applied to a first and a second threshold adjustment circuit. Each circuit adjusts the threshold depending on the respective values of the previous decisions, while the first circuit provides the adjustment based on an assumption that the next decision to be made will have a first signal value and the second circuit provides the adjustment based on an assumption that the next decision will have a second signal value. When that next decision becomes available, it is utilized to select the correct adjusted threshold value for the next comparison by the magnitude comparator.

Abstract: A data transmission apparatus is capable of data transmissions with and/or without error control. A remote data transmission apparatus with error control recognizes whether or not the carrier sent from the data transmission apparatus is intermittent. Additionally, the data transmission apparatus recognizes, based upon the existence of interruptions of a carrier signal sent from a remote data transmission apparatus, whether or not the remote data transmission apparatus has an error control function.

Abstract: A digital synchronizer examines a signal transmitted at a predetermined baud rate for a predetermined time. Upon completion of the predetermined time, a decision is made as to whether or not the signal included the predetermined baud rate. If the signal includes the predetermined baud rate, a bit clock is established indicative of the boundaries and center of each baud symbol. The synchronizer samples the signal at a multiple of the baud rate and accumulates the phase relationship between the samples and transitions of the signal during the predetermined time. Upon conclusion of the predetermined time, the distribution of the phase relationships is examined and the presence or absence of signal is determined. If the presence is determined, the bit clock is established.

Abstract: A signal generator for generating pulse signals having a waveform required by the Recommendation of International Telegraph and Telephone Consultative Committee (CCITT) is disclosed. The signal generator utilizes two D/A converters whereby the limitation of the operable frequency of the D/A converters restricts the variation rate of the output pulses. Each D/A converter provides the converted analog signal to the pulse transformer at timings different from one another. The pulse transformer detects the difference between the provided analog signals and provides a pulse signal having the required waveform. The difference of the output voltages between the two D/A converters varies at two times the operable frequency rate of the D/A converters, resulting in the pulse signals changing at a rate exceeding the operation frequency of the D/A converters.

Abstract: A threshold value control system for discriminating an input signal received by a receiver circuit is provided having a mode setting unit for determining a mode setting signal corresponding to a connection pattern of the receiver circuit. A variable threshold generating unit generates a variable threshold which varies depending on the variation of the level of the input signal. A constant threshold value generating unit generates at least one constant threshold by which the level of the input signal can be discriminated even when its level cannot be distinguished by the variable threshold value. A threshold comparing unit compares the variable threshold and each of the at least one constant threshold to output a comparison result.

Abstract: A jitter canceller cancels time-variant signals in telephone lines resulting from 50 or 60 Hz commercial power sources which a phase locked loop will fail to absorb. The jitter canceller uses an adaptive filter having a tap coefficient which is not reset to "0" and forced to converge before a data transmission allowing use with telephone lines with multiple modems connected to a single line. The jitter canceller uses a phase rotating circuit, two phase difference detectors, and the adaptive filter to rotate the phase of an incoming signal by a phase predicted by the adaptive filter in order to cancel jittering.

Abstract: A rectangular array of signal points forming a QAM signal point constellation is modified by relocating signal points from adjacent corners of the rectangular array to positions extrapolated from the rectangular array and at reduced distances from the origin, corresponding to reduced peak amplitude levels. The location is effected in a manner to maintain, at least for a majority of the relocated points, a Hamming distance of one. To this end for a constellation of 2.sup.2n+1 points, with n=4 or more and points with I and Q amplitudes 1, 3, 5 . . . units in the rectangular array, a plurality of points in each quandrant are relocated to positions, relative to positions which they would have in the rectangular array, rotated through an angle of 180.degree. about a point having I and Q amplitude co-ordinates of (2.sup.n, 2.sup.n).

Abstract: A line driver for a cable linked LAN maintains a high impedance across the cable when not sending data. A pulse transformer includes a primary and secondary winding. The primary winding of the transformer is placed between a first pair of transistors and a second pair of transistors. An array of switching inverters activates these transistors in such a manner whereby, when one pair is turned on, the other pair is turned off. This "off" and "on" toggling of the transistor pairs drives current into the transformer primary. Such current induces a pulse in the transformer secondary which is coupled into the LAN cable.