Abstract: A modulation system and associated method therefor for synthesizing a modulated signal. Information is converted into an in-phase signal portion and a quadrature signal portion. The two signal portions are combined by summation and difference operations, and the results are stored in registers. A multiplexer samples the resultant values stored in the registers wherein each register is sampled at least once during a period defined by a frequency of a carrier. The output of the multiplexer is a synthesized, modulated signal.

Abstract: A device including a comparator (3) each input of which receives signals from an information transmission line (1, 2) through a capacitor (4, 5), is characterized in that devices for forced switching (6) are interposed between the information transmission lines (1, 2) and the inputs of the comparator (3), the output of the latter being connected to one input of an OR gate (7) whose other input receives a reinitialization signal from a protocol decoder and whose output is connected directly and through an inverter to the device for forced switching (6) in order to reinitialize the comparator when the latter is blocked in a dominant state following interference.

Abstract: A control circuit (10) controls a voltage controlled oscillator (15) to cause the signal at the output of the oscillator to have slopes of frequency variation in accordance with biphase encoded data to be transmitted. The control circuit (10) limits abrupt frequency shifts in the oscillator output signal by inverting a sign multiplying the slope of frequency variation, utilizing an amplifier (50) with a controllable inversion state, in response to whether the state of the data to be transmitted, and a state, indicative of whether a frequency control voltage exceeds a zero threshold at sampling instants synchronous with the biphase data, are the same or different.

Abstract: The invention relates to filtering a periodic digital signal having N logic levels and having noise superposed thereon. The instantaneous probability of existence of each of these logic levels is converted into a corresponding one of N signals each having its own maximum amplitude when the modulated value of the received instantaneous signal is equal to the normal value for a corresponding logic level, which amplitude falls off by application of a weighting coefficient as the received instantaneous value moves away from the normal value of that logic level. The signal relating to each looked-for logic level is integrated over the duration of an elementary modulation period in the received digital signal, and the recognized logic level is the level corresponding to the largest value integral.

Abstract: A method is described for transmitting digital data with minimum splatter and for recovering the same with a conventional frequency modulated (FM) receiver to obtain data having minimum intersymbol interference. The method utilizes an optimized prototype pulse which has been predistorted to match the inverse characteristics of the post detection low pass filter in a conventional FM receiver. When the optimized electric pulse is received and processed by the post detection low pass filter of the conventional FM receiver, a pulse shape exhibiting minimal intersymbol interference is produced.

Abstract: A phase locked loop circuit is arranged such that the frequency of an input reference clock signal is selected on the basis of a first or second transmission rate of an incoming digital signal, whereby an output digital signal correctly synchronized with the incoming digital signal having the first or second transmission rate can be transmitted. Also, the phase locked loop circuit is arranged so that a first or second central frequency value and a first or second boundary frequency value are set in response to the first or second transmission rate of the incoming digital signal so that, if a frequency value of an output digital signal lies outside of a range of the first or second boundary frequency values, the frequency of the output digital signal is set to the first or second central frequency values. Thus, the phase locked loop circuit of the invention can deliver the output digital signal correctly synchronized with the incoming digital signal having the first or second transmission rate.

Abstract: A system is disclosed that provides for the proper decoding of data information in an Encoder-Decoder ENDEC receiver in a Fiber Distributed Data Interface FDDI network. The system decouples the receiver from the data information when idle signals are provided thereto. In so doing "fragment bytes" associated with such transmission are not decoded.

Abstract: A method for the equalization of dispersive, linear or approximately linear channels for the digital signal transmission by using an adaptive matched filter matched to the entire transmission channel, which converts the received signal into a time-discrete signal sequence and during this process determines the optimum sampling times by itself, and by the use of a subsequent equalizer which equalizes the signal sequence in sections by an iteration method with relaxation is disclosed.

Abstract: An image signal processing system DPCM encodes the signal, then Huffman and run length encodes the signal to produce variable length code words, which are then tightly packed without gaps for efficient transmission without loss of any data. The tightly packing apparatus has a barrel shifter with its shift modulus controlled by an accumulator receiving code word length information. An OR gate is connected to the shifter, while a register is connected to the gate. Apparatus for processing a tightly packed and decorrelated digital signal has a barrel shifter and accumulator for unpacking, a Huffman and run length decoder, and an inverse DCPM decoder.

Abstract: Described is a circuit arrangement that aligns the receiver of a communications device with the bit boundaries of a serially received data stream. The circuit arrangement delays a bit in a synchronized data stream and correlates it with a next bit in the data stream. If the bits are equal, a signal is generated to reset a synchronization latch. Thereafter, the receiver is synchronized to the incoming data.

Abstract: Disclosed is an apparatus for receiving a selected channel of a signal having a plurality of channels, each channel having a plurality of subchannels. A parabolic reflector, low noise amplifier and block converter receive the signal. A tuner detects the selected channel in the received signal and provides a detected signal corresponding to the selected channel. A demodulator demodulates the detected signal into a baseband signal corresponding to the selected channel, the baseband signal being modulated with the subchannels of the selected channel. An analog bus is connected to the demodulating means for providing the baseband signal. A first demodulator connected to the analog bus demodulates a first subchannel of the subchannels of the baseband signal and provides a signal representative of the first subchannel. A second demodulator connected to the analog bus demodulates a second subchannel of the subchannels of the baseband signal and provides a signal representative of the second subchannel.

Abstract: A quadrature coder for a two-wire digital loop communication system is described in which data is sampled and quadrature encoded by being divided into two bit streams, one of which comprises every other bit in the original bit stream and the other one comprises the remaining bits. One of the divided bit streams is delayed by 90.degree. from the other. The delayed and undelayed bit streams are then recombined and transmitted over a two-wire loop.

Abstract: An asynchronous communications device includes a dual port memory, means for inputting data into the dual port memory, and means for outputting data from the dual port memory, the device being configured to operate in a receive mode or a transmit mode according to its connection in a communications system. Suitably the device includes a built-in test facility for both the transmit mode and the receive mode. Preferably a clock frequency of 80 MHz is used for the operation of the device, and a 40 MHz clock signal is used to derive the 80 MHz clock frequency, the 80 MHz frequency being formed by four 20 MHz clock frequencies arranged with their rising edges 90.degree. out of phase. There is also provided a method of producing a clock frequency by utilizing four clock pulses with their rising edges 90.degree. apart.

Abstract: A device for the simultaneous division of a bandpass signal s(t)=x(t) cos .omega.ot-y(t) sin .omega.ot, .omega.o being an arbitrary angular velocity, into its components x(t), y(t), according to two carriers in quadrature cos .omega.ot and -sin .omega.ot at the angular velocity .omega.o, including a filter (3) for filtering the signal s(t), analog transform circuitry (8;25,26) for producing the Hilbert transform s(t) of the input signal s(t) provided in at least one of the channels of the device, a first sampler (6;21) for sampling the input signal s(t) and a second sampler (9;22) for sampling the Hilbert transform s(t), the samplers being controlled at a sampling frequency fe supplied by a sampling oscillator, fe being not less than 2F, F being the difference between fo=.omega.o/2.pi. and the frequency of the spectrum of the filtered input signal s(t) which is most distant from fo, and two analog-digital converters (7,10;23,24), associated with each sampler (6,9;21,22).

Abstract: In a multipoint data communications system used with analog communications channels that may insert undesirable frequency offsets in a modem carrier frequency, a slave modem that adjusts its transmit carrier frequency compensates for the offset influenced communications channel. A central modem device does not have to train up to slightly offset frequencies when the communications channel is effectively removing the offset added by a slave modem at its transmitter site.

Abstract: A mapping technique for an 8D, sixty-four state convolutionally coded 19.2 Kbit/second modem utilizes twenty-nine bits for defining all points of an 8D constellation. The 8D constellation which is mapped is comprised of a desired subset of a concatenation of four 2D constellations, where each 2D constellation has one hundred sixty points. The mapping technique generally comprises: dividing each 2D constellation into five different energy groups of thirty-two points each, the concatenation of four groups, one from each 2D constellation, comprising an 8D grouping; choosing five hundred twelve 8D groupings from the possible six hundred twenty-five (5.sup.

Abstract: In a signal distribution system, a bus transmission path is provided on which at least one terminal of a pair of transmission lines terminates in a proper potential through a line-to-ground characteristic impedance Z.sub.0. A pair of differential output terminals of at least one transmission circuit are connected to the corresponding pair of transmission lines on the bus transmission path to deliver differential transmission signals of a fundamental frequency f as output signals. A pair of differential input terminals of a respective one of a maximal number of reception circuits, N, are connected to the corresponding pair of transmission lines through a corresponding pair of branch resistors. The input terminal of the respective reception circuit has a characteristic of an input impedance Z.sub.L given below:Z.sub.L =R.sub.L +1/j2.pi.fC.sub.Lwhere R.sub.L and C.sub.L represent an effective resistive component and capacitive component, respectively, of the reception circuit. Here the values R.sub.1, R.sub.

Abstract: The invention involves an apparatus for recovering the carrier signal in OPSK or QAM data. First an energy directed phase detector controls a voltage controlled oscillator so that the output signal has a phase that is within a few degrees of the carrier phase. Following this coarse acquisition, the system clock timing is recovered and established. A decision directed phase detector, using the system clock information, then controls the VCO to adjust the output signal phase to within a very small tolerance of the actual carrier phase.

Abstract: A method for generating a clock for data receiving correctly synchronized in each bit even if received data in a paging receiver gets trembled or a duty period of the received data changes. Further, the method detects a duty change of receiving data by counting a period of a corresponding bit during a predetermined number of bits of receiving data. The clock generated is received with correct data in response to the duty change by detecting the duty change of the receiving data and by controlling the clock to a direction of short duty period upon the duty change of receiving data.

Abstract: The present invention relates to an apparatus for transmitting and receiving Manchester coded digital data for IEEE 802.3 Ethernet/Cheapernet type local area network. The apparatus mainly comprises, an isolation transformer, a signal converter with one end connected to one side of the isolation transformer, a receiver with its input connected to the other end of the signal converter, a capacitor located in the receiver and a transmitter with its output connected to the other side of the isolation transformer whereby the isolation transformer and the capacitor may isolate the external terminals from the main circuit. Moreover, the receiver and the transmitter can be integrally formed with a controller and thus to reduce the cost.