Abstract: A voice-band signal processor uses a DSP to filter digital transmit and receive voice-band signals, and has oversampling D/A and A/D converters with a frequency converter to convert between the oversampling rate and the DSP rate. An interpolator converts the filtered receive voice-band signal to a pseudo-analog signal that can be sampled by a demodulator in synchronization with a regenerated receive sampling clock, thus enabling correct operation even when the transmit and receive sampling clock rates do not match. In addition, the voice-band signal processor contains a status register circuit connected to flag registers in the DSP, enabling a host computer to read and set flag values that control the operating mode of the voice-band signal processor. The voice-band signal processor can thus be switched between half duplex and full duplex operation, or between different bit rates.

Abstract: An apparatus provides patterns for visually aiding an operator in determig the nature and noise environment of the incoming signal. A conventional signal receiver and an oscilloscope are coupled to a pair of phase detectors, a clock circuit, a reference circuit, and a timing circuit. The clock circuit synchronizes the operation of the receiver, reference circuit, and timing circuit. The phase detectors have pair of inputs and an output with the inputs of one detector being connected to the receiver and the reference circuit, and its output is connected to the Y deflection axis of the oscilloscope screen. The inputs of the other detector are connected to the receiver and the output of the reference circuit via a preselected analog time delay, and its output is connected to the X deflection axis of the oscilloscope screen.

Abstract: A network is synchronized by a hierarchical adjustment and the individual exchanges are equipped with frequency monitors for the reference frequencies that synchronize them, which, when activated, switch the center to another reference frequency or change it to the hold-over mode. When one of these exchanges is resynchronized, the rate-of-change of its reference frequency output signal of its central clock pulse generator is limited so that no frequency alarms are triggered in downstream exchanges synchronized by this exchange.

Abstract: A serial data communication device of a half-duplex communication system includes two communication units. One of the communication units has a counter for measuring a length of a remaining time during one sending/receiving period set for one-way data transmission (a period during one sending/receiving period W from the time when the communication unit receives all the send data from the other communication unit to the time to start data sending). A send frequency in data sending is determined to as a lower value practicable in the range in which no collision of the data occurs, depending on the length of the measured remaining time. The other communication unit is configured so as to receive the send data of one communication unit to extract the send frequency in synchronization with a serial clock signal having the same frequency as the send frequency and send the data.

Abstract: A modem implementation a high data transmission rate is implemented by means of pulse width modulation. The timing magnitude for each baud is weighted by the binary value of the data input. Minimal components are employed and the entire circuit is comprised of digital components except for a few analog components including a comparator for detecting transitions in the received pulse width modulation signal. This modem is particularly applicable to digital transmission of a digital video picture data via telephone lines to implement a video telephone. The video picture along with the synchronization signals from a video source are digitized and stored in a memory. The video telephone operates by sending and receiving by pulse width modulation both the video data and the synchronization signals.

Abstract: A data communications receiver for use in a modem. A fixed sample clock and a dominated tap tracking algorithm lock the local baud timing in the receiver to the baud timing in a remote transmitter. An interpolating filter provides a plurality of discrete delays. A filter control circuit inspects the tap coefficients of an adaptive equalizer to determine the location of and any movement of the dominant tap. The filter control circuit selects the rate of cycling through the discrete delays to compensate for any frequency difference between the local baud timing and the remote baud timing, and to prevent movement of the dominant tap. A baud detector circuit monitors the sample clock and the operating state of the filter control circuit to identify the end of a baud and detects and corrects for any frequency difference between the remote baud timing and the local baud timing by providing one additional sample or one less sample to the adaptive equalizer.

Abstract: A preprocessing unit is inserted between a baseband converter and an equalizer/detector for performing a signal processing which corresponds to a phase rotation of the CPM-signal in the baseband represented by in phase and quadrature components. The phase rotation progresses in discrete steps of 90.degree. per bit interval of the binary data signal contained in the CPM-signal. The introduction of the preprocessing unit renders it possible to use a comparatively simple conventional equalizer/detector for binary pulse amplitude modulated signals (PAM-signals) for equalizing and detecting binary CPM-signals received in distorted form. When the equalizer/detector is adaptive, a further preprocessing unit is inserted between a channel estimator and adjusting inputs of the equalizer/detector.

Abstract: A delay generator having very high accuracy and stability over temperature variations and time, suited for very short delay times, such as in clock recovery circuits in very high-speed digital data transmission systems. A delay line, having one end either open or shorted and a round-trip delay time of .tau., is driven by a voltage source, the output impedance thereof matched to the delay line, and a current source. The current source and the voltage source are driven by an input signal to be delayed. The voltage source is provided by a transistor operating as a voltage follower, which also operates to provide as an output a signal dependent on the difference between the input signal and the voltage on the delay line. This output serves as the output of the delay generator, the input signal delayed by a the time .tau..

Abstract: A method and apparatus for digitizing and transmitting one or more analog signals simultaneously over a two-wire line. The two-wire line not only provides the power required for the digitizing circuit and sensor, but is used also to transmit the analog information in a digital pulse train encoded with the power supply current. All data pulses are transmitted as the quiescent current of each analog coder module and its associated transducers connected to it. These data pulses start and end by transmission of a digital sync current pulse which separates transmission of each analog data pulse. The width of each data pulse conveys the desired information. A circuit for generating the pulse train having only two amplitudes but pulses having a variable width includes an SR flip-flop coupled to the output stage.

Abstract: A self-oscillating burst mode transmitter transmits an integral number of cycles of a carrier signal in each transmission burst. Each burst commences at a peak value of the carrier signal and terminates at a peak value. The transmitter includes an L-C tank circuit comprising a transmitting coil (L1) connected to a capacitor (C4). The L-C tank circuit is selectively energized through a switching network (Q1, Q2, U1, U2) connected to a power source, causing the tank circuit to resonate at a prescribed frequency (f.sub.0). Selective energization of the tank circuit is achieved by the switching network as controlled by a peak voltage detection circuit (32, 34). The peak detection circuit senses when a peak voltage is present in the oscillatory waveform appearing across the coil of the resonating tank circuit. Power is switched off to the tank circuit at the conclusion of each transmission burst only when the oscillatory voltage waveform, as sensed by the peak detection circuit, is at a peak.