Abstract: The present invention is directed toward a method and apparatus in a communications device for mapping a selected group of data bits into a predetermined number of two-dimensional symbols selected from a minimized alphabet of M two-dimensional symbols forming a symbol constellation, with one of the two-dimensional symbols being transmitter during each symbol (i.e., baud) interval. A plurality of symbol mappers in an adaptive communications device use a superframe of bits per baud. Each superframe includes at least two groups of frames, a low bit frame and a high bit frame. The superframe has A) one of these two types of frames uses whole bits per baud and the other uses fractional bits per baud or B) both of these two types of frames will use fractional bits per baud.

Abstract: A modem is connected to a terminal equipment and couples to another modem via a transmission line. The modem includes a data transmission and reception part for making data transmission and reception with the terminal equipment, and a modem part for determining a modulation technique, for modulating a transmission signal from the other modem. In addition, the modem includes a data compression and decompression part for determining a compression technique. The compression technique is used for compressing serial data from the data transmission and reception part before supplying the same to the modem part and for decompressing the compressed serial data from the modem part before supplying the same to the data transmission and reception part.

Abstract: A phase equalizer in the receiver portion of a bi-directional communication system is disclosed equalizer for reducing precursor intersymbol interference without any substantial degradation in signal to noise ratio. The phase equalizer is implemented as a switched capacitor filter having a clock (switch) rate at least four times the data baud rate and a z-transfer function T(z) of a form: ##EQU1## wherein G, A, and B are fixed but adjustable coefficients.

Abstract: A demodulator for coherent demodulation of a .pi./4 shifted QPSK signal includes a -.pi./4 phase-shift circuit in a conventional QPSK signal decision/feedback type Costas loop to alternately rotate the phase of an inputted .pi./4 shifted QPSK signal by 0 and -.pi./4 for each symbol period interval from a timing controller, thus eliminating the .pi./4 shift component of the .pi./4 shifted QPSK signal. Thus, coherent detection demodulation for the .pi./4 shifted QPSK signal having stable points at intervals of .pi./2 phase angles is enabled.

Abstract: An apparatus automatically corrects for DC offset in a multi-level packet-switched receiver. A reference carrier frequency is used during the receiver's idle mode to establish a DC offset exiting a discriminator (302). The DC offset is amplified by a video amplifier (315) and fed into an error amplifier (320) which generates the negative of the DC offset. The DC offset and the negative of the DC offset are input into a summing network (330) resulting in a zero DC offset exiting the video amplifier (315).

Abstract: A frequency detection system is based on a digital phase locked loop, the detection system being especially suitable for use in noisy environments like supervisory audio tone (SAT) detection in AMPS and TACS mobile telephone systems. In addition to the digital phase locked loop (4), the frequency detection system according to the invention incorporates a detector circuit (5), which comprises a detection timer (6) and two phase detectors VI1 (7) and VI2 (8). The timer (6) forms a detection sequence of desired length, at the end of which the output signal (SATVAL) of the detector circuit is updated. The first phase detector VII (7) has a phase window in which it counts those falling edges of the synchronized input signal (SSAT) that coincide with the window. The second phase detector VI2 (8) also has a phase window of its own in which it counts those falling edges of the synchronized input signal (SSAT) that coincide with its window.

Abstract: A circuit arrangement for channel-specific processing of a multi-channel input signal which may consist of two types of encoded signals, a first type wherein all channel signals are encoded by a bit-oriented method (e.g., delta modulation) and a second type wherein all channel signals are encoded by a character-oriented method (e.g., PCM). An interface process (SSP), to which the input signal is applied, is coupled to a bidirectional interface (BIS) for signals of the first type and which is controllable by means of write and read addresses, and is also coupled to at least two such bidirectionally controllable interfaces (BI0, BI1, . . . BI7) for signals of the second type. The latter interfaces are respectively coupled to respective transcoder processors (AP0, AP1, . . . AP7). One or more data outputs of the interface (BIS) for signals of the first type are respectively coupled to respective ones of the transcoder processors (AP0, AP1, . . . AP7).

Abstract: Disclosed is a method of selecting a relatively high reliability signal path between a mobile communication unit and a number of possible base sites.

Abstract: A facility is provided for measuring the signal-to-noise ratio of a transmission channel using the results obtained by transmitting over the channel a pseudorandom noise signal, in which the value of the signal-to-noise ratio may be used to determine whether the channel contains various types of pulse code modulation equipment.

Abstract: In a method of adjusting the phase of a clock generator with respect to a data signal (50) an auxiliary signal (52) is generated by comparing the data signal (50) and a clock signal (51). The auxiliary signal (52) exhibits a disuniform representation corresponding to various data bit sequences. The data sequences are detected and combined with the auxiliary signal to generate a phase adjustment signal (54) with a uniform representation corresponding to the various data bit sequences and having an average value depending upon the phase difference between clock signal and data signal. Further, a reference signal (55) may be generated, representing the average value of the phase adjustment signal (54) which responds to ideal phase state. This reference signal (55) in combination with the phase adjustment signal (54) may be used for an even more precise adjustment of the phase of the clock generator with respect to the data signal.

Abstract: An upper and lower side-band generator comprised of a combination of combinational logic circuits. In a preferred embodiment the invention utilizes a substantially square wave sync output associated with carrier and modulator signal generators. A lower side-band signal is generated by synchronizing the transitions of a modulator signal with the transitions of a carrier signal, mixing the synchronized signal with the carrier signal, and filtering the resulting mixed signal. An upper side band signal is generated by synchronizing the carrier and modulator signals, delaying the resulting synchronized signal, and mixing the delayed, synchronized signal and the carrier signal.

Abstract: The field of the invention is that of data processing modules placed in a receiver of a data transmission or emission network, and charged with the equalizing and time-pulse recovery of the received data, in order to furnish to the next elements of the chain of the receiver a clear signal with a clean and resynchronized clock phase.The objective is to provide a device extending the limits of restoring the service in the case of strong disturbances of the channel.

Abstract: A modulator circuit for generating a modulated, DQPSK signal. The modulator circuit includes an encoder for receiving a binary bit stream comprised of bit pairs defining differential phase changes. An encoder receives a bit stream of which bit pairs thereof define differential phase changes. The encoder encodes the bit pairs into codewords which are stored and then supplied to an I-accumulator, a Q-accumulator, and a memory element. The memory element contains pre-multiplied values which are supplied to the I- and the Q-accumulators which add terms of the pre-multiplied values to form I-portions and Q-portions of a DQPSK-modulated signal. The I- and Q-portions may then be supplied to a quadrature modulator.

Abstract: Asynchronous command data are converted to synchronous data by a synchronizer comprising a toggle flip-flop which receives the asynchronous command data to produce a pair of true and complementary outputs in response to a transition of the command data. A first NOR gate is responsive to the command pulses and the true output of the toggle flip-flop to produce a train of first pulses, and a second NOR gate is responsive to the command pulses and the complementary output of toggle flip-flop to produce a train of second pulses. First and second sampling flip-flops are connected to the outputs of the first and second NOR gates, respectively, to sample the first and second pulses therefrom in response to a trailing edge transition of a clock signal with a frequency twice as high as the nominal maximum frequency of the command pulses.

Abstract: A decoder for recovering an analog signal from its digital representation produced by an encoder employing adaptive-delta-modulation first decodes audio bit-stream (17) in the digital domain with digital delta demodulation (15), to a pulse-code-modulation (PCM) format digital signal. Post-processing (35), complementary to encoder processing is performed digitally on the PCM signal. The output from post-processor (35) is up-sampled, and using delta modulation, a noise shaped single-bit highly oversampled output is produced by converter (14). Applying the single-bit output to lowpass filter (11) re-constructs the decoded analog signal, which is audio output (12). By fully exploiting digital signal processing techniques, the decoder can be manufactured at low cost and exceed the performance of existing analog implementations.

Abstract: A voice frequency communication apparatus which is capable of detecting and processing the voice frequency terminal signal and non-voice frequency terminal signal and is also capable of realizing communication with ordinary voice frequency terminal signal and non-voice frequency terminal signal without erroneous changeover of the signal processing path because of always monitoring the sending/receiving data with CPU because of providing the constitution to always monitor the sending/receiving data by providing a central control circuit (CPU) having the constitution to always monitor the digital signal output of the detection circuit having the fuction to convert, when the analog input signal is non-voice frequency terminal signal, such non-voice frequency terminal signal into the digital data signal after detecting such signal and to convert, on the contrary, the digital data signal into the analog non-voice frequency terminal signal and the digital data signal to be input from the digital communication line

Abstract: A digital GPS (Global Positioning System) receiver for receiving a plurality of coded satellite signals. The plurality of satellite signals are transmitted by a corresponding plurality of satellites. Since these satellites are moving rapidly with respect to the receiver, Doppler shifting of the signals is exhibited. The signals are converted from analog to digital at intermediate frequency levels. The signals are then separated simultaneously into a plurality of digital signals corresponding to I and Q channel information for each transmitting satellite. A processor then converts these I and Q channel information signals to pseudo-range and broadcast data for navigation and time purposes.

Abstract: An adaptive predistortion circuit with memory for a digital transmission system includes a set (10) of input registers storing various consecutive data symbols a predistortion circuit (11) for predistorting the data of the consecutive data symbols before they pass through a modulator (14) and then through an amplifier (15) and an adaptation circuit (19) which, in response to a demodulation (16, 17.sub.1, 17.sub.2, 18.sub.1, 18.sub.2) of the stream of transmitted data symbols continuously adapts the predistortion circuit (11) to the stream of input data symbols. The adaptation circuit (19) includes a set (21) of counters/accumulators which determine the center of gravity of the smeared spots (clouds) created by the distortion by calculating a set of errors that is used for adapting the predistortion circuit (11). Preferably, the predistortion circuit is a random access memory.

Abstract: A subscriber unit for wireless communication with a base station in a wireless subscriber communication system includes a FIR chip, a DIF (digital intermediate frequency) chip, a single processor chip and a radio. The processor chip transcodes a digital voice input signal to provide digital input symbols; demodulates an output signal received from the base station to provide digital output symbols; and synthesizes a digital voice output signal from the digital output symbols. The FIR chip FIR filters the digital input symbols and generates timing signals for timing the transcoding and synthesizing operations in the processor chip. The DIF chip digitally synthesizes a digital intermediate frequency signal by direct digital synthesis (DDS) and modulates the digital intermediate frequency signal with the filtered input symbols to provide a modulated intermediate frequency input signal. The radio further processes the modulated input signal for transmission to the base station.

Abstract: Jitter attenuators (100) with a phase detector (104) to control a crystal oscillator to remove jitter wherein the phase detector includes both a sequential phase/frequency detector (200) of low transistor count and an arrangement of two sequential phase/frequency detectors (198 and 200) to increase gain and two drivers for the crystal oscillator.